EMC concepts explained
Estimating the Parasitics of Passive Circuit Components
T
his article presents a simple method of estimating the parasitics of the three passive circuit components (R, L, C). First, the non-ideal model of each component is presented, followed by the network analyzer measurements. The component (approximate) model serves as the basis for analytical calculations leading to the values of the parasitics.
The PCB used in this study, [1], is shown in Figure 1.
Figure 1: PCB and its details
Since the calibration traces are of the same length as the traces leading to the components, the connectors and traces are effectively taken out of the measurements. Thus, the measured parasitics come from the component itself and not from the connecting traces. It should be noted that this approach is not targeting the impedance measurement accuracy but rather provides the simplest way of estimating the component parasitic values. More accurate methods exist [2-5].
1. Resistor Model and Its Parasitics
Circuit model and the impedance vs. frequency curve (straight-line approximation) for a resistor and its parasitics (with no traces attached) are shown in Figure 2 [6,7].
Figure 2: Resistor circuit model and its impedance curve
Figure 3 shows the measurement setup used to obtain the impedance curves for three different resistor values.
Figure 3: Measurement setup – resistor impedance curves
Resistor impedance curves are shown in Figure 4.
Figure 4: Resistor impedance curves
Each curve shows a 3-dB point corresponding the frequency (shown in Figure 1):
From Equation 1, the parasitic capacitance can be obtained as:
The resulting parasitic capacitance values for the three resistors are shown in Table 1.
Table 1: Resistor – parasitic capacitance
2. Capacitor Model and Its Parasitics
Circuit model and the impedance vs. frequency curve (straight-line approximation) for a capacitor and its parasitics (with no traces attached) are shown in Figure 5 [1,2].
Figure 5: Capacitor circuit model and its impedance curve
Figure 6 shows the measurement setup used to obtain the impedance curves for three different capacitor values.
Figure 6: Measurement setup – capacitor impedance curves
Capacitor impedance curves are shown in Figure 7.
Figure 7: Capacitor impedance curves
Each curve shows a self-resonant point corresponding the frequency (shown in Figure 5):
From Equation 3 the parasitic inductance can be obtained as:
The resulting parasitic inductance values for the three capacitors are shown in Table 2.
Table 2: Capacitor – parasitic inductance
3. Inductor Model and Its Parasitics
Circuit model and the impedance vs. frequency curve (straight-line approximation) for an inductor and its parasitics (with no traces attached) are shown in Figure 8 [1,2].
Figure 8: Inductor circuit model and its impedance curve
Figure 9 shows the measurement setup used to obtain the impedance curves for three different inductor values.
Figure 9: Measurement setup – inductor impedance curves
Inductor impedance curves are shown in Figure 10.
Figure 10: Inductor impedance curves
Each curve shows a self-resonant point corresponding the frequency (shown in Figure 9):
From Equation 3 the parasitic inductance can be obtained as:
The resulting parasitic capacitance values for the three inductors are shown in Table 3.
Table 4: Inductor – parasitic capacitance
References
- Haring, D., designer of the PCB used in this study
- https://www.mwrf.com/technologies/test-measurement/article/21849791/copper-mountain-technologies-make-accurate-impedance-measurements-using-a-vna
- https://www.clarke.com.au/pdf/CMT_Accurate_Measurements_VNA.pdf
- https://passive-components.eu/accurately-measure-ceramic-capacitors-by-extending-vna-range
- https://www.w0qe.com/Measuring_High_Z_with_VNA.html
- Adamczyk, B., Teune, J., “Impedance of the Four Passive Circuit Components: R, L, C, and a PCB Trace,” In Compliance Magazine, January 2019.
- Adamczyk, B., “Basic Bode Plots in EMC Applications – Part II – Examples”, In Compliance Magazine, May 2019.
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Dr. Bogdan Adamczyk is professor and director of the EMC Center at Grand Valley State University (http://www.gvsu.edu/emccenter) where he regularly teaches EMC certificate courses for industry. He is an iNARTE certified EMC Master Design Engineer. Prof. Adamczyk is the author of the textbook “Foundations of Electromagnetic Compatibility with Practical Applications” (Wiley, 2017) and the upcoming textbook “Principles of Electromagnetic Compatibility with Laboratory Exercises” (Wiley 2022). He can be reached at adamczyb@gvsu.edu.
Nick Koeller is an EMC Engineer at E3 Compliance which specializes in EMC & SIPI design, simulation, pre-compliance testing and diagnostics. He received his B.S.E in Electrical Engineering from Grand Valley State University and is currently pursuing his M.S.E in Electrical and Computer Engineering at GVSU. Nick participates in the industrial collaboration with GVSU at the EMC Center. He can be reached at nick@e3compliance.com.
Megan Healy is pursuing her Bachelor of Science in Electrical Engineering and Bachelor of Arts in German Language at Grand Valley State University. She currently works full time as an Electromagnetic Compatibility Engineer co-op student at E3 Compliance, which specializes in EMC and high-speed design, pre-compliance, and diagnostics. She can be reached at megan.healy@e3compliance.com.