EMC concepts explained
Eye Diagram

Part 1: Fundamental Concepts


his is the first of two articles devoted to an eye diagram. In this article, the fundamental definitions and concepts are presented. The next article will show the impact of driver, receiver, and interconnect properties on signal quality using data eye and data eye mask concepts while evaluating several different HDMI cables.

Consider a digital signal as it travels from a transmitter to a receiver. The quality of the signal arriving at the receiver can be affected by many factors, including the transmitter, cables or PCB traces, and connectors. The signal quality is also referred to as signal integrity. An eye diagram is a graphical tool used to quickly evaluate the quality of a digital signal. The name eye diagram has been coined because it has the appearance of a human eye [1,2]. Eye diagrams are commonly used for testing at both receivers and transmitters.

An eye diagram is basically an infinite persisted overlay of all bits captured by an oscilloscope to show when bits are valid. This provides a composite picture of the overall quality of a system’s physical layer characteristics. This picture covers all possible combinations of variations affecting the signal: amplitude, timing uncertainties, and infrequent signal anomalies.

The eye diagram is created by superimposing successive bit sequences of the data. Consider all possible 3-bit sequences shown in Figures 1a through 1h.

It should be noted that the data sequences in Figure 1 and Figure 2a are shown as straight lines; the actual data stream looks like the one shown in Figure 2b.

multiple graphs illustrating 3-bit sequences (a-h), and eye diagram (f)
Figure 1: 3-bit sequences (a-h), and eye diagram (f)
two line graphs; left: (a) Ideal bit sequences, right: (b) actual bit sequences
Figure 2: (a) Ideal bit sequences, (b) actual bit sequences
Eye Diagram Parameters
Ideally, the eye diagram would consist of two parallel horizontal lines and two parallel vertical lines (assuming instantaneous rise and fall times), as shown in Figure 3a. Assuming a more realistic case with finite rise and fall times, the less “ideal” eye diagram would look like the one shown in Figure 3b.

An even more realistic signal would exhibit some degree of amplitude and rise/fall time variation. These amplitude and time variations give rise to several parameters associated with an eye diagram, as shown in Figure 4 on page 50.

Note that the eye area has been reduced. The eye crossing in Figure 4 is often referred to as a zero crossing since the data used for an eye diagram creation is usually transmitted as a differential pair signal.

The eye diagram shown in Figure 4 is still an “ideal” diagram, as it consists of perfectly straight lines. An actual (real data) eye diagram looks more like the one shown in Figure 5 on page 50.

two "Ideal" eye diagrams; left: (a) instantaneous rise and fall times, right: (b) finite rise and fall times
Figure 3: “Ideal” eye diagram – (a) instantaneous rise and fall times, (b) finite rise and fall times
graphic of eye diagram parameters
Figure 4: Eye diagram parameters
image of an actual eye diagram
Figure 5: Actual eye diagram
Data and Clock Dependencies
To achieve high reliability of data transfer, a synchronization signal is introduced. This signal is used to trigger data transfer operation. The data transfer occurs when the synchronization signal transitions its state (e.g., the rising edge of a clock signal), at which time the data signal state will be read as either low or high. The high state will be read when the data signal is above a certain voltage threshold level (VIL max), and it will be read as low when it is below another voltage threshold (VIH min). This synchronization signal is typically referred to as a clock or strobe.

However, data signal voltage levels being below or above a predefined voltage threshold at the time of data transfer is an insufficient condition for reliable data transfer. It is also necessary to meet certain timing dependencies between data and synchronization signals.

To explain those dependencies, let’s look at a specific case described in Figure 6 [3]. The synchronization signal, in this case, is the clock and the data is transferred (read) at the rising edge of the clock. We will assume that the clock and data signals are transitioning very quickly.

To guarantee that the proper data will be read, a valid data signal must be present for a certain time duration prior to the clock signal transition. This duration is referred to as a setup time (tSETUP). Additionally, it is also required that the data signal remains valid for a certain time duration after the transition of the clock signal. This duration is referred to as a hold time (tHOLD). Setup and hold times are properties of devices receiving the data and are often referred to as their timing requirements. If the timing requirements are not met, incorrect data can be read by the receiver.

graphic illustrating data and clock synchronization for signals with fast transition times

Figure 6: Data and clock synchronization for signals with fast transition times

graphic illustrating data and clock synchronization for signals with slow transition times
Figure 7: Data and clock synchronization for signals with slow transition times

Using midpoint signal levels, the assumption of very fast signal transitions allows us to measure timing dependencies between the data and clock (setup and hold time). In other words, this assumption means we can neglect signal rise/fall time duration if those durations are much shorter than the duration when the data bit is valid. Suppose the clock period gets shorter, and we can no longer neglect signal rise/fall time duration. In that case, the evaluation of timing dependencies between the data and clock (setup and hold time) must account for slow signal transition. Figure 7 illustrates such a case.

The rising edge of the data is still very fast, but the clock transition is much slower. The duration of time between the clock transition from low and high level is now substantial compared to the duration of the data bit. During this long clock transition time the clock state can be either high or low, so we no longer can measure setup and hold time using midpoint levels. This case would require setup and hold time to be measured when the signals are crossing the low or high voltage threshold levels (VIL max, VIH min).

Evaluation and visualization of valid signal timing using the setup and hold time shown in Figure 6 is relatively easy, even with the clock and data jitter.

It is, however, quite difficult for the case shown in Figure 7 when taking jitter into account. That’s where the eye diagram can help.

Data Eye Mask
The concept of a data eye diagram can be used to evaluate the quality of the data signal and whether the signal meets timing requirements. To accomplish this, receiver timing requirements are used to define the horizontal dimension of a region. Voltage level thresholds (VIL max, VIH min) are used to define the vertical boundaries of that region. The resulting region is referred to as the data eye mask. A sample of a data eye mask, representing requirements for a video HDMI standards receiver, is shown in Figure 8.

The data eye mask represents the “keep-out” region. Signals at the receiver must not cross the data eye mask region, or a violation of receiver timing requirements occurs. The mask is defined based on receiver properties and can have various shapes (rectangular, triangular, etc.). The data eye mask can be many different shapes, as shown in Figure 9.

graphic illustrating HDMI data eye mask
Figure 8: HDMI data eye mask
four graphs illustrating examples of data eye masks
Figure 9: Examples of data eye masks
Future Work
The next article will show the impact of driver, receiver, and interconnect properties on signal quality using data eye and data eye mask concepts.
  1. Herres, D., “The Eye Diagram: What is it and why is it used?” Test & Measurement Tips, August 2016.
  2. Behera, D., et al., “Eye Diagram Basics: Reading and Applying Eye Diagrams,” EDN, December 2011.
  3. Micron TN-48-09: LVTTL Derating for SDRAM Slew Rate Violations.
Bogdan Adamczyk headshot
Dr. Bogdan Adamczyk is professor and director of the EMC Center at Grand Valley State University (http://www.gvsu.edu/emccenter) where he regularly teaches EMC certificate courses for industry. He is an iNARTE certified EMC Master Design Engineer. Prof. Adamczyk is the author of the textbook “Foundations of Electromagnetic Compatibility with Practical Applications” (Wiley, 2017) and the upcoming textbook “Principles of Electromagnetic Compatibility with Laboratory Exercises” (Wiley 2022). He can be reached at adamczyb@gvsu.edu.
Headshot of Krzysztof Russa
Krzysztof Russa is a Principal Engineer at E3 Compliance LLC. He leads High-Speed design efforts related to Signal and Power Integrity challenges. Years of experience in the design industry with balanced use of simulation and measurement techniques have been recognized by awarding him three times the International Mentor PCB Technology Leadership Award. He can be reached at krzysztof.russa@e3compliance.com.
Headshot of Nicholas Hare
Nicholas Hare is pursuing his Bachelor of Science in Electrical Engineering at Grand Valley State University. He currently works full time as an Electromagnetic Compatibility and Signal Integrity Engineering co-op student at E3 Compliance, which specializes in EMC and high-speed design, pre-compliance, and diagnostics. He can be reached at nicholas.hare@e3compliance.com.