n Part 1 of this series, we introduced embedded detection technology, which augments basic protection against ESD events, and explored the opportunities for embedded ESD detection solutions.
Protection sets the fundamental thresholds for a device’s robustness. In contrast, detection broadens the device’s awareness around these limits, helping it identify potential issues such as data corruption, immediate damage, or the cumulative effects of ESD within these thresholds. Armed with this, the designer has an opportunity to design in recovery functionality rather than just accept a mysterious malfunction.
Here, in Part 2, we shift our focus to the practical aspects of implementing embedded ESD detection. We’ll provide a step-by-step guide, discuss validation and testing methodologies, present case studies, and delve into future trends and innovations in the field.
- Soft-Reset: When a system successfully survives an ESD zap, the HBM or CDM on-chip protection may trigger its on-board power supply clamps that short VDD to VSS to minimize voltages throughout the chip. (See Figure 1.) Once the pulse has dissipated, the power rails will return to their pre-zap levels and may trigger Power-on Reset (POR) circuits, resetting the system. If the firmware is aware that an ESD event has been detected just before POR has occurred, then the software can take additional remedial and recovery actions.2
- System Lockup: As with a soft reset, when the on-chip protection occurs, the logic state and coherency cannot be trusted. In fact, the MCU or Crystal Oscillator may run “off into the weeds” and require a hard power cycle, which may not be possible in mission-critical and medical devices. However, embedded ESD detection logic can recognize the event and “kick start” the device back to life. If the software is written in such a way that the user does not notice this disruption, then such an upset has been effectively eliminated from an IEC qualification failure list without board spins, etc.
- Data Corruption: Any software programmer assumes that when a value is written to a location, it will be there when it is read back. However, after an ESD event, memory and registers, program counters, and stacks can be altered slightly or obliterated. This can sometimes create a latent “soft error,” which might not manifest itself for days or operation. An ESD event detector can alert the program to recheck the system state and restore corrupted areas or at least throw an error alert.
- Latent Circuit Damage: Even a survivable strike may significantly degrade component lifetimes.3 A system that has weathered 10,000 pulses is not necessarily as healthy over time and temperature as a system that has never been struck.
- TVS Optimization: By recording and perhaps transmitting ESD event telemetry back to the manufacturer, system designers can fine-tune the protection levels, potentially reducing cost by optimizing for the actual ESD levels the products are seeing in the field.
As opposed to the simple level detector in [4], this circuit allows the reconstruction of the actual shape and spectral content of ESD pulses entering a chip.
These early examples of embedded detection have been complimented by the ongoing innovation and development in embedded on-chip ESD detection applications. As ICs continue to evolve and geometries shrink, these technologies may play an active role in preventing further technology nodes from becoming almost unusable due to ESD soft errors and upsets.
- W. Huang, J. Dunnihoo, and D. Pommerenke, “Effects of TVS integration on system level ESD robustness,” EOS/ESD Symposium, Reno, NV, 2010, pp. 1-6.
- White Paper 3 System Level ESD Part I: Common Misconceptions and Recommended Basic Approaches (v1.0 December 2010). https://esdindustrycouncil.org/ic/en/documents/white-paper-3-system-level-esd-part-i-common-misconceptions
- I. Laasch, H-M. Ritter and A. Werner, “Latent damage due to multiple ESD discharges,” EOS/ESD Symposium, Anaheim, CA, 2009, pp. 1-6.
- N. Jack and E. Rosenbaum, “Voltage monitor circuit for ESD diagnosis,” EOS/ESD Symposium Proceedings, Anaheim, CA, 2011, pp. 1-9.
- F. Caignet, N. Nolhier, A. Wang, and N. Mauran, “20 GHz on-chip measurement of ESD waveform for system-level analysis,” EOS/ESD Symposium, Las Vegas, NV, 2013, pp. 1-9.