oughly a decade ago, starting at 22nm technology nodes, the transistor architecture changed from planar to FinFET [1-3]. Bulk FinFET (FF) which is a multi-gate transistor built on Si substrate has been the mainstream in the state-of-the-art logic CMOS technologies for many mobile SoC applications [1-3]. Fortunately, ESD reliability has not been an obstacle in the FinFET era from 22nm to 5nm technology nodes. Nowadays, with the increased requirements of high-performance computing applications, logic CMOS technologies need further evolutions. Several new transistor architectures have been proposed to achieve more powerful computing capability. In this article, we will look at the impacts of these transistor architectures on ESD reliability.
In addition to the new GAA transistor architecture, the integration of a Source/Drain (S/D) dual epitaxy process with strain engineering [3, 12-15] has been proposed to continuously enable better, faster, and more compact devices [13]. For example, in p-type MOSFETs, the Si S/D epitaxy structure is replaced by a SiGe S/D epitaxy structure [13-15] for providing the channel strain engineering. These examples of architecture and material options can bring critical challenges of ESD reliability.
One measure of ESD performance in these new device structures is to characterize diodes as a way of assessing their impact. Prior research has shown the investigations of ESD diodes in SOI and bulk FinFET technologies [16, 17]. ESD diodes in bulk Si GAA vertically-stacked horizontal nanowires (NW) technology have been also reported [18]. In addition, the impact of the material options with SiGe S/D epitaxy on the bulk FF ESD diode performance has also been shown [15, 19]. In this article, the influence of the SiGe epitaxy stressor on bulk GAA NS ESD diodes will be disclosed.
One outcome in the architecture change from FF to GAA NW, due to a different fin height (Hfin) in these two technologies, is that the ESD diodes have different thermal behaviors. A taller fin structure usually has a large epitaxial volume on the anode and cathode regions [18]. This improves the thermal dissipation and results in less self-heating and lower Ron under 100ns TLP stress. However, this taller fin architecture with a reduced fin pitch can result in a smaller contact area at the S/D regions due to the S/D epitaxy growth and the middle-of-line (MOL) process modules, which can impact ESD diode failure levels, as illustrated in Figure 3. With a Hfin of 50nm and a fin pitch (Pfin) of 45nm, the S/D epitaxy growth between any two fins results in their adjacent epitaxy regions merging. This allows an increased area of the contact scheme in MOL local interconnect (LI) processes, as shown in Figure 3a. The contact scheme depth (Dcon) is defined by the top of a Silicon (Si) epitaxy structure and the bottom of a LI recess ending depth in ILD0 layer. With a reduced Pfin of 30nm, the Si epitaxy structure between two fins will be merged, resulting in a reduced contact depth (D’con), as shown in Figure 3b. Taller fins with a further reduced Pfin will have more merged epitaxy volume. The contact scheme along the fin length has been shown to impact It2 [17]. The reduced Dcon can be expected to bring a negative impact on ESD diode performance, increasing its thermal heating under ESD and hence lower failure current. Fortunately, the original fin pitch in sub-5nm GAA NS technology can be relaxed from the industrial 7nm/5nm FF technologies [10]. Therefore, the impact of S/D material options on ESD diode performance can be more critical in GAA NS technologies.
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