EMC concepts explained
Crosstalk between PCB Traces –
Time and Frequency Domain Measurements
Part 1: Impact of the PCB Topology
By Bogdan Adamczyk, Mathew Yerian-French, and Ryan Aldridge
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his article is the first of a two-article series devoted to the topic of crosstalk between PCB traces. This topic was previously discussed in [1] and [2]. In [1], we used a first-generation PCB and concentrated on signal integrity or the time domain measurements. In [2], we used a redesigned PCB to show the time domain impact of the guard trace on crosstalk. This two-article series presents measurements taken with a third-generation PCB. These measurements were taken both in the time domain using an oscilloscope and in the frequency domain using a near-field H probe. In Part 1 of the series, we vary circuit topology, i.e., the distance between traces and the distance to the ground plane. Both the time domain and frequency domain measurements show (for the topologies tested) that bringing the ground plane closer to the signal plane has a larger impact on reducing crosstalk than increasing the distance between traces. In Part 2 (to appear in the next issue), we investigate the impact of guard trace on crosstalk reduction, both in time and frequency domains.

Crosstalk Circuit Model
When two circuits are in the vicinity of one another, a signal propagating in one circuit can induce a signal in another circuit due to capacitive (electric field) and/or inductive (magnetic field) coupling between the circuits [1,2]. This phenomenon is referred to as crosstalk. An example of such an arrangement and its circuit model is shown in Figure 1.
a diagram depicting microstrip line PCB configuration and its circuit model
Figure 1: Microstrip line PCB configuration and its circuit model

Two PCB traces in a microstrip configuration are separated from each other by a distance s and from the ground plane (which is a return conductor for both) by a distance d. The first trace (generator conductor) is driven by a time-varying voltage source VS with the impedance RS and terminated by a load resistor RL. The second trace (receptor conductor) is terminated by the load resistors RNE and RFE on the near end and the far end, respectively.

Superposition of the inductive and capacitive coupling mechanisms results in the receptor circuit shown in Figure 2, where LGR and CGR represent the mutual inductance and mutual capacitance, respectively, between the generator and receptor circuits (this model is valid for electrically short structures).

diagram illustrating the receptor circuit model in time domain
Figure 2: Receptor circuit model in time domain
The near- and far-end voltages in the time domain are given by [1,2]
Equation 1a
Equation 1b
Equation 1 reveals several important aspects:
  1. If VS = const, then VNE(t) = 0 and VFE(t) = 0.
  2. A faster rise or fall time, dVS /dt, results in larger values of VNE(t) and VFE(t).
  1. On the rising edge of VS(t), dVS /dt > 0, and both the inductively and capacitively induced near-end voltages are positive; VNE,ind > 0, VNE,cap > 0.
  1. On the rising edge of VS(t), the inductively induced far-end voltage is negative, VFE,ind < 0, while the capacitively induced far-end voltage is positive, VFE,cap > 0.
On a microstrip PCB, the inductive coupling usually dominates the capacitive coupling [3] and, thus, the far-end voltage, on the rising edge of VS(t) is usually negative.
Time Domain Measurement Setup
The measurement setup for time domain crosstalk measurements is shown in Figure 3.
an experimental setup for time domain measurements
Figure 3: Experimental setup for time domain measurements
Three different circuit topologies were investigated and are described in Table 1.
table listing circuit topologies
Table 1: Circuit topologies
Figures 4 through 6 show the generator signal, VS, as well as the resulting near-end voltage, VNE, and far-end voltage, VFE, induced in the receptor circuit.
graph results of crosstalk induced voltages – Case 1
Figure 4: Crosstalk induced voltages – Case 1
graph results of crosstalk induced voltages – Case 2
Figure 5: Crosstalk induced voltages – Case 2
graph results of crosstalk induced voltages – Case 3
Figure 6: Crosstalk induced voltages – Case 3
The source signal is an open-circuit voltage of 0-5 Vpp, 1-MHz trapezoidal pulse train having 100-ns rise time, 200-ns fall time, and a 50% duty cycle.
Case 1 Observations
Voltage induced at the near end during the rise time is VNE = 6.4 mV. while the voltage induced during the fall time VFE = -3.2 mV. Since the value of the rise time is twice that of the fall time, according to Equation 1a, the induced voltages should differ in magnitude by a factor of two, which indeed is the case. We also note that the polarities of the two voltages are opposite, which is to be expected from Equation 1a. Similar observations can be made for the voltages induced at the far end. Furthermore, since the coefficients of coupling for the near-end voltage (Equation 1a) are positive, the induced voltage during the rise is also positive. The far-end voltage is negative during the rise time, indicating that the inductive coupling dominates the capacitive one (see Equation 1b).
Case 2 Observations
Increasing the distance between the traces from 30 to 60 mils while keeping the distance to the ground plane unchanged reduces both the NE and FE voltages.
Case 3 Observations
Decreasing the distance to ground reduces both the NE and FE voltages. The impact of bringing the ground closer to the signal layer is larger than the impact of increasing the distance between traces.
Frequency Domain Measurement Setup
The setup for the near-field H-probe measurements is shown in Figure 7.
an experimental setup for frequency domain measurements
Figure 7: Experimental setup for frequency domain measurements
The source signal had the same parameters as in the time domain setup, except for the rise and fall times, which were set to 10 ns. The H-field probe in the near field scanner took measurements at 9 MHz and 49 MHz.

Figure 8 shows the measurement results at 9 MHz, while Figure 9 shows the results at 49 MHz. These measurements are summarized in Table 2.

H-field measurement results at 9 MHz
Figure 8: H-field measurement results at 9 MHz
H-field measurement results at 49 MHz
Figure 9: H-field measurement results at 49 MHz
table listing near field measurement summary
Table 2: Near field measurement summary
Observations
Increasing the distance between the traces from 30 to 60 mils while keeping the distance to the ground plane unchanged reduces the near-field intensities. Decreasing the distance to ground also reduces the field intensities. The impact of bringing the ground closer to the signal layer was larger than the impact of increasing the distance between traces. The frequency domain results are consistent with the results obtained in the time domain.
References
  1. Bogdan Adamczyk and Jim Teune, “Crosstalk Reduction between PCB Traces,” In Compliance Magazine, March 2017.
  2. Bogdan Adamczyk, Principles of Electromagnetic Compatibility: Laboratory Exercises and Lectures, Wiley, 2024.
  3. Howard Johnson and Martin Graham, High‑Speed Digital Design – A Handbook of Black Magic, Prentice Hall, 1993.
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headshot of Dr. Bogdan Adamczyk
Dr. Bogdan Adamczyk is professor and director of the EMC Center at Grand Valley State University (http://www.gvsu.edu/emccenter) where he performs EMC educational research and regularly teaches EM/EMC courses and EMC certificate courses for industry. He is an iNARTE-certified EMC Master Design Engineer. He is the author of two textbooks, “Foundations of Electromagnetic Compatibility with Practical Applications” (Wiley, 2017) and “Principles of Electromagnetic Compatibility: Laboratory Exercises and Lectures” (Wiley, 2024). He has been writing “EMC Concepts Explained” monthly since January 2017. He can be reached at adamczyb@gvsu.edu.
headshot of Mathew Yerian-French

Mathew Yerian-French is an electrical engineer specializing in EMC design and diagnostic testing. He received his B.S.E in Electrical Engineering from Grand Valley State University. He focuses on preventing EMC issues through design reviews and early EMC pre‑compliance testing and diagnostics. Mat participates in the industrial collaboration with GVSU at the EMC Center. He can be reached at mathew.french@e3compliance.com.

headshot of Ryan Aldridge
Ryan Aldridge is the Operations Manager for Grand Valley State University’s Innovation Design Center. He works closely with Prof. Adamczyk, developing EMC educational material, and assists him with GVSU’s EMC Center. He attended Grand Valley State University for his bachelor’s and master’s degrees in electrical and computer engineering.
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