2.5D/3D Integration Challenges: Bare Die Testing

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Part 2

By Nathaniel Peachey and Brett Carn on behalf of EOS/ESD Association, Inc.

art 1 of this series introduced the ESD risks posed by 2.5D/3D chiplet integration and outlined the ESDA’s Class 1 and Class 2 framework, along with the contact-based CDM test methods currently being evaluated for Class 2 devices.

Beyond determining the contact-first CDM test method, other challenges remain for both Class 1 and Class 2 chiplets, some of which are even more critical for Class 1 chiplets. These additional challenges include:

Correlation to FICDM
Failure criteria
Determination of rise time for contact-first CDM methods

Statistical sampling techniques
EDA tool demands for verification

Let’s briefly discuss each as they relate to Class 2 and Class 1 chiplets.

The industry has long used FICDM to evaluate the robustness of semiconductor devices; a shift to a contact-first CDM test method will naturally introduce correlation challenges that will impact both Class 1 and Class 2 chiplets. Because the device is pulsed rather than discharged, it is not clear whether there will ever be a perfect correlation.

Failure criteria have always been based on automated test equipment testing the packaged device for both parametric and functional content. Since the CDM testing of Class 2 chiplets involves probing of the bare die, evaluation of the functional operation of the die after the contact-first CDM test will be difficult at best. Class 1 chiplets offer even more of a challenge, as mechanical probing is not possible, and therefore, functional testing becomes even more challenging.

The rise time of the contact-first CDM test method is another challenge. In an FICDM discharge, the rise time is determined by factors such as the spark resistance, pogo pin inductance, device/package capacitance, humidity, and the geometry of the discharge point. However, in a contact-first CDM test, a fixed-rise-time pulse will be delivered that will likely not match the rise time seen in an FICDM test and will be affected by factors that are different from those affecting the waveform generated by FICDM. The rise time could be faster or slower, but it will very likely be different. The rise time during a CDM discharge experienced by a Class 2 chiplet may differ from that of a Class 1 chiplet, depending on factors such as the chiplet size (Class 1 potentially being larger) and the manufacturing tools used for each chiplet class.

Abstract 3D graphic of a futuristic microchip processor hovering above a blue circuit board.

Typically, Class 2 die-to-die (D2D) interfaces in a chiplet can number in the hundreds to perhaps in the tens of thousands. Using a contact-based CDM test method may be practical for testing several hundred to perhaps a thousand D2D interfaces, but tens of thousands will likely drive the need for some form of sampling that has yet to be defined. This may also be true for EDA tools, which are verifying the ESD protection on each D2D interface. Looking at Class 1 chiplets, this challenge is compounded by the fact that D2D interfaces on these chiplets could number in the tens of thousands to hundreds of thousands, underscoring the need for some form of sampling, not only in testing but also in verification using EDA tools. Due to the large number of D2D interfaces, these Class 1 chiplets would also place a significantly greater burden on EDA tool verification accuracy and coverage, especially if a “correct-by-design” approach is used, as discussed in Part 1.

Summary

In summary, the transition to 2.5D and 3D heterogeneous integration is driving a fundamental shift in how ESD robustness must be evaluated at the chiplet level. Traditional CDM test methods are increasingly inadequate for the fine geometries and low withstand voltages of modern devices, necessitating the development of new contact-based techniques and, in some cases, a shift toward design-centric verification approaches. While viable paths are emerging for Class 2 chiplets, significant gaps remain for Class 1 technologies, where physical testing may not be feasible. Addressing these challenges will require continued industry collaboration to refine test methodologies, establish meaningful correlations and failure criteria, and enhance EDA tool capabilities to ensure reliable system-level performance in next-generation integrated designs.

References

Kathleen Muhonen, “Small Form Factor CDM Testing, Part 1: Problems with FICDM Testing for Small Form Factor and Interface Die,” In Compliance Magazine, January 2026.
Kathleen Muhonen, “Small Form Factor CDM Testing, Part 2: Air Discharge Options,” In Compliance Magazine, February 2026.
Kathleen Muhonen, “Small Form Factor CDM Testing, Part 3: Contact First Methods,” In Compliance Magazine, April 2026.
JEDEC JEP 196, “White Paper 2 Part II: Die‑to‑Die Interfaces,” Industry Council on ESD Target Levels, November 2023.
ANSI/ESD SP5.3.4-2022 “Charged Device Model (CDM) Testing Component Level – Capacitively Coupled Transmission Line Pulsing (CC-TLP) as an Alternative CDM Characterization Method,” 2022. https://www.esda.org
ANSI/ESD SP5.3.3-2018 “Charged Device Model (CDM) Testing – Component Level Low‑Impedance Contact CDM as an Alternative CDM Characterization Method,” 2018.
Nathaniel Peachey and Brett Carn, “2.5D/3D Integration Challenges: Bare Die Testing, Part 1,” In Compliance Magazine, October 2026.

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The Authors
Nathaniel Peachey serves as ESD Engineering Manager at Qorvo, leading development of ESD solutions and PDK libraries for Qorvo’s technologies. As current Senior Vice President of the ESD Association board, he holds 13 patents and is a Senior IEEE Member.

Brett Carn, now retired after 38 years in semiconductors, remains active with ESDA as Standards Strategic Manager, overseeing all standards. He chairs the Technical and Advisory Support Committee, leads ESDA Online Training, and received the 2023 Outstanding Contributions Award.

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