Figure 3 and Figure 4 show 2kV HBM simulations and 500V CDM simulations results of those ICs respectively. The simulation results fully correlate with the actual failure mechanism observed in both the RF (Figure 3) and the mixed-signal (Figure 4) ICs. Also, a very good correlation is found between the CDM simulation and measured CDM waveforms from the JS-002 verification modules. These modules correspond to the so-called ESDA small coin (with a capacitance of about 4.0pF) and large coin (with a capacitance of about 30.0pF). They both make use of the FR-4 material.
- D.A. Smolyansky, “TDR Techniques for Characterization and Modeling of Electronic Packaging,” High-Density Interconnect Magazine, 2 parts (TDA Systems, Application Note PKGM-0101), March and April 2001.
- Dolphin Abessolo-Bidzo et al., “CDM Simulation Based on Tester, Package and Full Integrated Circuit Modeling: Case Study,” IEEE Trans. on Electron Devices, vol. 59, pp. 2869 – 2875, November 2012.
- Dolphin Abessolo-Bidzo et al., “A Study of HBM and CDM Layout Simulations Tools,” Electrical Overstress/Electrostatic Discharge Symposium Proceedings, paper 5B.2, 2018.
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