Tackling Low-Voltage Signaling in Inverter Design: Part 1

Feature Article

Managing High-Power Inverter Noise to Protect Low-Voltage Signals

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ot long ago, the electrification of consumer machinery was primarily limited to hybrid electric vehicles (HEVs), marketed as the next generation of clean propulsion but largely out of reach for the average consumer. Now, with the advent of affordable, high-end microcontroller units (MCUs) and high-efficiency semiconductors, the adaptation of motor control has become more accessible, expanding electrification into secondary markets such as turf care and agricultural equipment, in addition to a growing HEV market. This shift means that embedded system or module development engineers are encountering new challenges associated with electric drives.

Central to these advanced systems are the power electronic components that constitute the inverter system. These components are responsible for converting DC voltage from a generator or battery into an appropriate signal to drive a three-phase motor. Designing and interfacing with the control electronics of inverters present unique challenges, particularly in managing signal integrity and mitigating noise. To illustrate these complexities, a typical inverter system is depicted in Figure 1.

Figure 1: Example diagram of a typical inverter system

A significant challenge in designing and interfacing with electric drives is managing signaling levels and their susceptibility to conducted electrical noise from the inverter’s output stage. However, with inverters switching hundreds of amps, the quest for high efficiency, module designers have optimized for minimal dead times, high drive strength, and fast edge rate; all of which come at the expense of electrical noise. These modules typically operate across a wide range of voltages, from 50V to several hundred volts, and at varying power levels tailored to specific applications. However, the signaling voltage levels, constrained by the process technology, generally range from 1.8V to 5.0V.

Balancing the need for the highest efficiency with typical voltage input output (V_IO) levels and ensuring that the controller can accurately manage the drive becomes a primary challenge for both embedded and analog engineers.

To better understand the challenges involved in designing, building, and debugging a high-power mixed-signal inverter, Part 1 of this two-part article will provide an in-depth discussion of the components and functions of an inverter. This includes examining common application-specific integrated circuits (ASICs) that work alongside field effect transistors (FETs) and MCUs, focusing on their roles in interfacing and driving. We’ll also address common functions such as communication and GPIO (general purpose input output) usage.

Identifying Common Low Voltage Signaling Interfaces

Interfacing between the MCU and external ASIC circuitry as sensitive traces is the first step in mitigating noise since each interface plays a specific role in the command and control of the module at the application layer. To better understand their functions and potential failure modes, the low voltage interfacing is categorized into the following groups of GPIO:

Inter-integrated circuit communication interface (I²C)/serial peripheral interface (SPI) communication lines—These are the most common types of communication interfaces, especially for advanced ASICs such as smart gate drive devices and external monitor circuitry. I²C operates with an open‑drain configuration, while SPI uses a push‑pull mechanism.

Low voltage drive signals—These signals are used for the command and control of drivers, typically driven by a timer circuit. They generally interface with a level shifter or gate driver that controls the motor.

Critical GPIO signals—These include fault processing signals used to quickly disable the drive, reset pins to alert the MCU of issues in the drive circuitry, and control pins for the ASIC’s functionality. Although less common, these signals are needed to obtain real time operational fault and drive status while under operation.

In any of the above scenarios, incorrect signal detection due to coupled noise from the power FETs can lead to challenges specific to that signal’s function. What makes these signals sensitive is the small signal-to-noise ratio they have, inherent in many ASICs and MCU interfacing structures. This vulnerability arises because ASICs tend to operate with low IO voltage (V_IO), typically on a CMOS level from either:

External V_IO—Interfaces with the MCU, allowing the ASIC to signal at voltages as low as 1.8 V; or

Internal V_IO—Logic levels designed around a 3.3V internal reference, a typical CMOS signaling level.

The noise generated by high-power switching transients is often comparable to these low signal levels. A transient that crosses the threshold for a long enough time (i.e., exceeds a deglitch time, or T_d) to trigger a logic switch results in incorrect actuation. To better understand how high levels of transients can affect IO signaling, it is essential to refer to the datasheet where the input high (V_IH) and low (V_IL) levels are defined.

Examining V_IH, V_IL from the Datasheet

When designing a signaling interface to an ASIC, engineers should first consult the datasheet for minimum, typical, and maximum values. These datasheet values are tested at manufacturing, and the ASIC manufacturer strives to not ship pieces that operate beyond these limits. The values define your operating parameters and edge cases where you want to stay away from:

V_IH—The voltage at which the input triggers a low‑to-high transition;
V_IL—The voltage at which the input triggers a high‑to-low transition; and

Minimum pulse width, debounce, or deglitch time—The minimum time a signal must persist above or below the voltage thresholds for a logic level threshold change.

Figure 2 illustrates typical 3.3v CMOS TTL gate-level input and output signaling.

Figure 2: V_IH/V_IL signaling levels for an input buffer

To assess how these logic levels impact noise tolerance, we must first investigate the structure of an input buffer representative of a standard CMOS input to an ASIC.

The model shown in Figure 3 depicts an input logic circuit referenced to a V_IO, primarily at DC. At the top of the input, we generally find V_IO or a reference voltage, either externally fed or internally generated. The key voltage levels are when the inverter circuit recognizes a logic high, with added hysteresis, and when it recognizes a logic low, again with hysteresis. When transient characteristics are introduced, trace parasitic can significantly impact circuit performance during coupled switching transients on the reference, power, or input lines.

Figure 3: Example of a buffer circuit inside the ASIC

Figure 4: The previous circuit structure with labeled parasitic and its impact on V_IH and V_IL levels

Additionally, the voltage levels defined in datasheets are typically guaranteed at DC, determined by slowly ramping a voltage signal up and down to obtain minimum, typical, and maximum values. If we apply a switching transient coupled onto either the inverter input, power, or ground, ringing can:

Collapse the power supply momentarily reducing your V_IH levels;
Bounce the reference (or ground) momentarily impacting V_IL levels;
or

Couple onto your input signal, causing an incorrect V_IH to be detected, or even worse, cause overshoot that the typical oscilloscope is not able to detect.

The impact of the transient’s scale with the speed and power of the switching signal. So the faster the transient, the more impact in terms of coupling, reference bounce, or power rail collapse.

After understanding how reducing V_CC or increasing the reference to your circuit can impact V_IH and V_IL values, the discussion can shift to how this noise impacts gate drive, I²C/SPI, and other GPIO signals that operate at CMOS levels.

Impact Of Noise on Gate Drive ASICs

The control strategy behind an inverter and how it creates AC power from DC is complex enough to fill a book. However, at its most basic level, the motor is controlled by filtering tightly controlled pulses through motor windings to create AC currents. Since the MCU isn’t capable of driving the output switches directly, a level shifter or a more commonly found gate drive ASIC is used (often labeled a “Smart” Gate Driver). A simplified diagram is depicted in Figure 5.

Figure 5: A simplified inverter system with gate drive

Applications that rely on gate drive ASIC performance generally employ features such as:

Monitoring the voltage and currents across the FETs—Ensuring that parameters are within safe operating ranges and provides protection when they’re not.
Automatic deadtime insertion—Preventing shoot-through by inserting a delay between turning off one transistor and turning on the complementary transistor.

PWM mode selection—Allowing the selection between 3 PWM (where opposite side drives are complementary, controlled by the gate driver circuit with trimmable deadtime insertion) or 6 PWM mode (where all low side PWM drive pulses are controlled by the MCU).

Despite the advanced functionality of the gate drive ASIC, it ultimately reacts to the low voltage side inputs. This means that if transient spikes on the input persist above the V_IH for longer than T_d, it will pass that pulse through to the high side of the gate driver. As a result, noise coupled onto the low voltage side of the device can manifest itself in several ways depending on how and where the noise is imposed onto the device IO.

If the noise voltage couples onto the low side PWM signals, it runs the risk of actuating the high side and low side at the same time. This could result in shoot through or shoot through protection, which occurs when both transistors conduct simultaneously, resulting in a temporary short circuit.

Gate drivers often include protection logic to prevent this, along with modification of deadtime to better control switching performance. The high‑side and low-side gate pulses control the switching of transistors that drive the e-machine and are generally complimentary to each other in 3-pwm mode, and in 6-pwm mode they are driven complimentary. Gate drive ASICs have functions and characteristics that manage these by automatically protecting the switches from short circuiting as well as automatic dead time insertion, along with calibratable drive strength.

The most common type of shoot through protection that ASICs employ is automatic early pulse termination. This, erroneously, happens either:

When bounce on the reference plane from opposite side switching pulse either lifts the reference high enough to trigger the opposite side, or creates a noise voltage spike, causing an early termination of the driving pulse; or

When a voltage transient larger than the V_IH threshold is detected at the input of the low voltage side. These transients are generally very difficult to measure accurately due to the parasitic of the probe and probe clip being able to be easily loaded. As such, they are generally estimated from a measurement of the ground or by overlaying a switching pulse.

Examples of a reference bouncing are shown in Figure 6.

Figure 6: (Left) Noise on the AGND reference net that should be 0v, (Right) gate pulses, the cause of the reference noise

In both pictures, the magnitude of the noise on the “AGND” net causes the reference to move, caused by the orange PWM signals on the picture to the right. When lined up properly, as outlined in the solid pink box, this can cause incorrect actuation of the neighboring low voltage signal in either incorrect triggering or a missed trigger.

This interaction leads to the diagram below depicting early pulse termination and its impact on the high voltage drive pulse. As the diagram in Figure 7 shows, the moment the noise voltage crosses the V_IH threshold, the pulse is terminated, deadtime is inserted, and the pulse is driven low, only to be driven high again when the transient event is over, causing erratic motor operation.

Figure 7: Example of early pulse termination due to the gate driver trying to prevent simultaneous high/low side actuation

In the event the gate driver ASIC does not have active protection, designers generally rely on complimentary parts of a circuit to drive the output in 3-pwm mode, where the low side turns on when the high side turns off. However, the issue still remains and is compounded because, while the pulses are complimentary of each other, they are still subject to trace capacitance, which can impact the propagation delay of the complimentary signal, which could cause accidental shoot through.

Next, we’ll focus on the impact of noise on I²C and SPI communication buses.

Impact of Noise on Common Communication Interfaces

While incorrect actuation on IO and drive signals is relatively easy to visualize, their impact on standard communication interfaces like I²C and SPI is more subtle and can create difficult-to-debug challenges. To better identify these issues, let’s briefly overview the interfaces:

I²C—I²C is a common hardware interface and protocol used to facilitate communication between ASICs and a controller MCU. The hardware is designed as an open-drain, pulldown circuit, which requires pullup resistors to the IO voltage level. Its idle state is typically pulled high, and it counts nine clock edges per 8 bits of data transferred. I²C uses two wires: a clock line and a data line, connecting the controller to its peripherals.

SPI— SPI is a common hardware-defined interface that functions as a shift register between the controller and peripherals. The hardware operates much faster than I²C, as it is a driven interface (commonly referred to as push-pull). SPI typically uses four wires: clock, data in, data out, and chip select.

The digital block in both of these communication interfaces typically features a state machine that counts edges when they receive the signal to begin a frame. The clock is specifically controlled by the controller in typical situations. If incorrect actuation occurs due to a high-power transient coupling onto either the clock or data lines, we risk encountering the following challenges:

Data corruption: When pulses on the data line aren’t read properly by the controller, data validation can be performed via CRC. If the CRC does not match, the frame is dropped. This method applies to both I²C and SPI.
Clock corruption: Clock corruption is more nuanced and depends on which part of the communication interface is impacted.

Near-end crosstalk: Noise coupled onto the clock signal near the controller can cause the controller to count extra clock pulses. This could lead to early termination or releasing of the bus while the peripheral device is still transmitting, leading to a stuck bus condition.
Far-end crosstalk: Noise coupled onto the clock signal near the peripheral device can cause the peripheral to count extra clock pulses. This could result in incorrect data being sent, or an error in communication between the peripheral and controller devices.

In all of these situations, the impact is again difficult to measure due to probe parasitic. In Figure 8, we can see what appears to be a good I²C transaction, but the result is a stuck bus line.

Example of an oscilloscope detected a proper I2C transaction, but the bus is held due to the ASIC not detecting the pulsetrying to prevent simultaneous high/low side actuation

Figure 8: Example of an oscilloscope detected a proper I²C transaction, but the bus is held due to the ASIC not detecting the pulsetrying to prevent simultaneous high/low side actuation

This situation resulted in the controller or peripheral clock counters becoming out of sync, incorrectly missing a clock pulse, even though an oscilloscope demonstrates otherwise. On a communication bus, this desynchronization can lead to a bus-stuck condition, where a device holds down either the clock or data, waiting for extra edges that will never come. Each situation requires software intervention to recognize the issue and release the bus.

Additionally, because each interface is controlled in a different circuit manner, they’re impacted differently. Since I²C is an open-drain interface, it is primarily impacted by reference bounce and pullup strength, especially during transitions. The pulldown is expected to be referenced to the same 0 V at both the near and far ends.

And while I²C is tolerant to a wide variety of pullup and duty cycle conditions, as shown in Figure 9, it is important to choose the right operating conditions.

Example of a I2C transaction with a very weak pullup, clock glitching, and narrow duty cycle still being detected properlytransaction, but the bus is held due to the ASIC not detecting the pulsetrying to prevent simultaneous high/low side actuation

Figure 9: Example of a I²C transaction with a very weak pullup, clock glitching, and narrow duty cycle still being detected properlytransaction, but the bus is held due to the ASIC not detecting the pulsetrying to prevent simultaneous high/low side actuation

As SPI is a push-pull interface, its impact is limited to glitches on either the clock or data lines during transmission, and typical errors here are in extra clock pulses inserted on the SCK (resulting in a stuck bus) or extra data pulses on either the serial out or serial in data lines (resulting in a corrupted packet).

While coupled transients can significantly affect GPIO drive signals and the communication interface to typical ASICs, we can now explore techniques and complementary circuits that can be implemented to mitigate these issues. In many situations, conducted electrical noise is inherent to the design of high‑power inverter systems. Mitigation strategies can be divided into two main categories:

Components used for impacting the sharp edges that are the source of electromagnetic interference; and

Layout and planning to ensure that the system has the best chance of avoiding issues by placing connectors and creating a stack up that shield low voltage circuitry.

Conclusion

With the push across various industries to hybridize machines that would otherwise be pneumatic or hydraulically driven, inverters are becoming prolific. The design challenges that come along with these inverters are often centered around the balancing of being robust to high voltage transients on low voltage signaling and switching efficiency in order to get the most out of the inverter. In Part 2 of this article, we’ll discuss the importance of choosing the correct PCB stack up during component selection and placement, including placeholders for components that otherwise can be unpopulated.

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Christopher Semanson is a System and Solution Engineer at Renasas Electronics America, Inc. in Durham, NC, supporting a wide variety of general-purpose applications dealing with microcontroller unit (MCU), memory protection unit (MPU), and electrical system design. He has previous experience in EMC Education at the University of Michigan, teaching EMC and Electronics with Mark Steffka and in Software Systems and John Deere and Ford Motor Company. Semanson has a bachelor’s degree in electrical and computer engineering and a master’s degree in electrical engineering from the University of Michigan Dearborn. He can be reached at chris.semanson@renesas.com.

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