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Challenges of CDM Modeling for High-Speed Interface Devices
T
he Charged Device Model (CDM) qualification level is essentially correlated to the peak ESD discharge current [1]. Hence, several modeling approaches have been proposed to predict CDM peak current for a given package and CDM voltage level based on lumped-element equivalent circuits [2, 3]. However, the behavior of ultra-high-speed interfaces is more complex, involving fast rise time waveforms and on-die transient phenomena that cause device failure at lower CDM levels [4]. Distributed parasitics models of both on-chip circuitry and package wiring are required to capture such phenomena properly.
State of the Art
Figure 1 shows the field-induced CDM tester schematic and the corresponding 3-capacitor circuit model described in the JEDEC standard [1]. The following capacitance contributions are considered in this model:
- Field plate to device under test (DUT) capacitor CDUT, considering the contribution of package conductors and on-die traces.
- Ground plane to DUT capacitor CDG, always significantly smaller than CDUT.
- Ground plane to field plate capacitor CFG, including the chassis contribution (separated in more complex 5-capacitor models [3]).
Figure 1: CDM tester scheme (left) and equivalent 3-capacitor circuit model (right) [1].
The equivalent circuit is then completed by the spark resistance, a series inductor accounting for the contributions of arc and pogo pin, and a 1 Ω current sensing resistance from pogo pin to ground. This model is suitable to describe the initial peak of the CDM discharge current, which has been shown to correlate well with the CDM failure threshold in many cases.
Problem Statement
However, when dealing with ultra-high-speed interface devices, the model described in the previous section yields a significant mismatch with respect to experimental data. To understand its limitations, consider the Spice schematic shown in Figure 2.
- The DUT is modeled as a lumped capacitor CDUT. This approach is suitable for peak current estimation but does not allow the evaluation of the actual voltage at the pad and the voltage drop on internal nodes (critical for deeply scaled, overshoot-sensitive technologies).
- With respect to the model shown in Figure 1, package trace and bonding impedance are modeled as a lumped RL series (Rpkg, Lpkg). However, the actual discharge channel behavior is more complex than an RL series, with reflections and delays that may affect the input waveform.
To overcome such limitations, distributed parasitics models are required to successfully predict the CDM behavior of ultrafast devices, providing a more reliable description of fast transient phenomena that can occur in the tester structure and within the DUT.
Figure 2: Spice implementation of the 3-capacitor circuit model.
Proposed Approach
The most sensitive victims for high-speed interfaces are thin gate oxides directly connected to the pad to optimize RF and high-speed performance. To assess the design solutions, a distributed DUT model, as presented in Figure 3 on page 44, can be plugged into the CDM tester model, replacing the lumped DUT capacitor. An example of a protection concept of a single-stage ESD diode protection with a power clamp (PC) is included in the model. The maximum voltage difference between Vdut and Vss (Vdd) should not exceed the breakdown voltage of the gates. On-die parasitics of Vss and Vdd nets strongly influence the actual voltage waveform at the input gate oxide. In particular, oscillations and spikes in the voltage waveform are sensed by the gate oxide and can lead to damage.
To account for the package trace behavior at fast transients as well, the lumped Rpkg and Lpkg need to be replaced by a more accurate channel model, capturing fast rise time slopes and possible reflections. Since the channel behavior strongly depends on the topology and layout of the substrate wiring, the most accurate modeling approach will require S-parameter extraction through calibrated EM simulations. However, a simple lossy transmission line (TL) already represents a good trade-off between accuracy and complexity, which can be included in the Spice model.
Figure 4 shows the comprehensive CDM tester model with two building blocks representing the distributed DUT model and the distributed discharge channel model (S-parameter or lossy TL).
Figure 3: Distributed DUT model including resistance and inductance parasitics. The NMOS and PMOS gates represent the sensitive victims.
Figure 4: CDM tester model with distributed DUT and channel.
A comparison of the current waveforms obtained with different models is shown in Figure 5, obtained with Vtest = -250 V. The simple lumped model yields a smooth current waveform flowing through Rsense (blue dashed curve). A similar current behavior is obtained when including a distributed DUT model while keeping the RL channel (orange curve). On the other hand, including a distributed channel model allows the capture of reflections and delays that affect the current waveform (green curve), with variations in slope that could affect rise time‑sensitive devices.
The voltage waveform at the input gate oxide can only be evaluated in the presence of a distributed DUT model. Hence, the following cases are considered in Figure 6:
These peak values must be compared against the gate oxide breakdown voltage to assess whether the device is able to withstand the targeted CDM stress. It clearly shows that the simple “lumped” model can be too optimistic for high-speed interfaces where ultrafast CDM transients can reach a thin gate oxide.
- To model the voltage without on-die parasitics, a distributed DUT model with no inductance and resistance contributions on Vdd and Vss branches is considered. This yields the smooth voltage waveform indicated as “lumped” DUT (blue dashed curve) with a low peak voltage below 4V.
- The presence of on-die parasitic resistance and inductance in the distributed DUT model leads to an additional voltage drop and increases the peak voltage to more than 6 V at the input gate oxide (orange curve).
- More severe voltage spikes up to 10 V are obtained by adding the distributed channel model on top (green curve).
These peak values must be compared against the gate oxide breakdown voltage to assess whether the device is able to withstand the targeted CDM stress. It clearly shows that the simple “lumped” model can be too optimistic for high-speed interfaces where ultrafast CDM transients can reach a thin gate oxide.
Figure 5: Current waveforms comparison.
Figure 6: Voltage waveforms at the gate oxide.
Conclusions
A simple lumped CDM tester model is suitable to evaluate the peak current at the I/O pads of the DUT for regular interface devices working at frequencies up to the low GHz range. However, fast transient phenomena such as current reflections and voltage overshoots can strongly degrade the overall CDM robustness when considering high-speed interfaces working at frequencies beyond 5 GHz. This is due to their capability to conduct ultrafast transients of the CDM pulse to the input gates. More complex distributed models are required to capture these phenomena, offering a methodology to assess the ESD performance of such designs.
References
- ANSI/ESDA/JEDEC JS-002-2022, “Joint Standard for Electrostatic Discharge Sensitivity Testing – Charged Device Model (CDM) – Device Level.” http://www.esda.org/standards/esda-documents
- Shukla, Vrashank, et al., “Predictive Modeling of Peak Discharge Current During Charged Device Model Test of Microelectronic Components,” 2013 35th Electrical Overstress/Electrostatic Discharge Symposium, IEEE, 2013.
- Atwood, Bruce C., et al., “Effect of Large Device Capacitance on FICDM Peak Current,” 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), IEEE, 2007.
- Ishfaq, Umair, et al., “Advanced CDM Simulation Methodology for High-Speed Interface Design,” 2022 44th Annual EOS/ESD Symposium (EOS/ESD), IEEE, 2022.
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Emanuele Groppo received his B.Sc. (2020) and M.Sc. (2022) in Electronic Engineering from Politecnico di Torino, Italy. He is currently pursuing a Ph.D. at the Technical University of Munich (TUM), Chair of Circuit Design. In 2023, he joined the ESD team at Intel in Munich, Germany. The focus of his research is on novel ESD devices and solutions for advanced semiconductor technologies.
Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.