EMC concepts explained
Impact of a Decoupling Capacitor and Trace Length on Signal Integrity in a CMOS Inverter Circuit
By Bogdan Adamczyk and Mathew Yerian-French
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his article describes a laboratory experiment that shows the impact of the decoupling capacitors and a PCB trace length on the signal integrity in a CMOS inverter circuit.

Switching Circuit Description
Figure 1 shows the block diagram of the switching circuitry.
Figure 1: Block diagram of the switching circuit
Figure 1: Block diagram of the switching circuit
A detailed schematic of the circuit is shown in Figure 2.
Figure 2: Schematic of the switching circuit
Figure 2: Schematic of the switching circuit
The PCB used in this experiment is shown in Figure 3.
Figure 3: Both sides of the PCB
Figure 3: Both sides of the PCB
The PCB used in this experiment is a newer version of the board used previously and described in [1]. This new PCB (designed by Mathew Yerian-French) contains several switches allowing the user to change the oscillator frequency, the length of power, and ground traces and choose whether to use the decoupling capacitors.

During switching, a transient current is drawn from the source. The inductance associated with the current loop causes the voltages at the power and ground pins to deviate from the desired values, as shown in the measurement section (see [1] for more details).

The board was purposely designed with very long traces to show the negative impact of the associated inductance while increasing the impact of a decoupling capacitor at the same time.

Impact of the Trace Length and Decoupling Capacitors: Measurements
The measurement setup is shown in Figure 4 (see [2] for the experiment details, Altium board files, and BOM).
Figure 4: Measurement setup
Figure 4: Measurement setup
Figures 5 and 6 show the voltages at the VCC pins of the inverters with respect to their GND pins. Figure 5 shows the results for short traces, while Figure 6 shows the results for long traces with no decoupling capacitors.
Figure 5: VCC-GND voltages – short trace, no decoupling capacitors
Figure 5: VCC-GND voltages – short trace, no decoupling capacitors
Observations: Both the amplitudes and duration of the ringing are larger for long traces as compared to short traces.
Figure 6: VCC-GND voltages – long trace, no decoupling capacitors
Figure 6: VCC-GND voltages – long trace, no decoupling capacitors
Figures 7 and 8 show the voltages at the VCC pins of the inverters with respect to their GND pins for short traces vs. long traces with a 0.1 µF decoupling capacitor at each inverter.
Figure 7: VCC-GND voltages – short trace, 0.1 µF decoupling capacitors
Figure 7: VCC-GND voltages – short trace, 0.1 µF decoupling capacitors
Observations: Decoupling capacitors dramatically reduce the ringing amplitudes and duration. The impact of the trace length is not as pronounced.
Figure 8: VCC-GND voltages – long trace, 0.1 µF decoupling capacitors
Figure 8: VCC-GND voltages – long trace, 0.1 µF decoupling capacitors
Figures 9 and 10 show the voltages at the GND pins of the inverters with respect to the main circuit input GND for short traces vs. long traces with no decoupling capacitors.
Figure 9: GND-GND voltages – short trace, no decoupling capacitors
Figure 9: GND-GND voltages – short trace, no decoupling capacitors
Observations: The duration of the ringing for long traces is significantly larger as compared to short traces. The amplitude of the ringing for long traces is, however, not as large as for short traces.
Figure 10: GND-GND voltages – long trace, no decoupling capacitors
Figure 10: GND-GND voltages – long trace, no decoupling capacitors
Figures 11 and 12 show the voltages at the GND pins of the inverters with respect to the main circuit input GND for short traces vs. long traces with a 0.1 µF decoupling capacitor at each inverter.
Figure 11: GND-GND voltages – short trace, 0.1 µF decoupling capacitors
Figure 11: GND-GND voltages – short trace, 0.1 µF decoupling capacitors
Observations: Decoupling capacitors dramatically reduce the ringing amplitudes and duration. The impact of the trace length is barely noticeable.
Figure 12: GND-GND voltages – long trace, 0.1 µF decoupling capacitors
Figure 12: GND-GND voltages – long trace, 0.1 µF decoupling capacitors
All measurement results are summarized in Table 1.
Table 1: Summary of the results
Table 1: Summary of the results
Future Work
The next column in the February issue describes the operation of an ideal difference amplifier.

The upcoming March 2024 column will discuss the impact of a decoupling capacitor and trace length on radiated emissions. Measurements will be performed in a semi-anechoic chamber, in accordance with CISPR 25 Edition 5 automotive standard, a monopole antenna was used in the frequency range of 150 kHz – 30 MHz, a biconical antenna in the range of 30 MHz – 300 MHz, and a log-periodic antenna in the range of 300 MHz – 1GH.

The April 2024 column will be devoted to conducted emissions measurements in accordance with the same standard. Measurements will be performed in the same semi-anechoic chamber, both on the battery and ground lines in the frequency range of 150kHz – 108 MHz.

References
  1. Bogdan Adamczyk, “Impact of a Decoupling Capacitor in a CMOS Inverter Circuit,” In Compliance Magazine, September 2019.
  2. Bogdan Adamczyk, Principles of Electromagnetic Compatibility: Laboratory Exercises and Lectures, Wiley, 2023.
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Bogdan Adamczyk headshot
Dr. Bogdan Adamczyk is professor and director of the EMC Center at Grand Valley State University (http://www.gvsu.edu/emccenter) where he performs EMC educational research and regularly teaches EMC certificate courses for industry. He is an iNARTE certified EMC Master Design Engineer. He is the author of the textbook Foundations of Electromagnetic Compatibility with Practical Applications (Wiley, 2017) and the upcoming textbook Principles of Electromagnetic Compatibility: Laboratory Exercises and Lectures (Wiley, 2024). He has been writing this column since January 2017. He can be reached at adamczyb@gvsu.edu.
Mathew Yerian-French
Mathew Yerian-French is an electrical engineer specializing in EMC design and diagnostic testing. He received his B.S.E in Electrical Engineering from Grand Valley State University. He focuses on preventing EMC issues through design reviews and early EMC pre‑compliance testing and diagnostics. Mat participates in the industrial collaboration with GVSU at the EMC Center. He can be reached at mathew.french@e3compliance.com.
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