Evaluation of PCB Design Options on Analog Signal RF Immunity using a Multilayer PCB

EMC concepts explained

Part 2: Radiated Immunity Testing

By Bogdan Adamczyk, Scott Mee, and Bilguun Baatar

his is the second of three articles devoted to the design, test, and EMC immunity evaluation of multilayer PCBs containing analog circuitry. The first article presented a top-level block diagram description of the design problem under research [1,2]. This article is devoted to the RF immunity testing according to the ISO11452-11 Radiated Immunity Reverberation Method standard from 400MHz – 1GHz, up to 100V/m. As a reminder, two analog measurements are present on the PCB. The first analog measurement captures analog temperature values from a Negative Temperature Coefficient (NTC) thermocouple at the end of a short harness. The second analog measurement captures the analog voltage of 12 volts connected at the banana jack terminals of the PCB. Both sets of values are processed by the microcontroller and reported to the test engineer outside the chamber via Universal Asynchronous Receiver Transmitter (UART) and fiber optic communications for isolation. However, for this article, only analog temperature measurements are presented and discussed.

1. PCB Variants and Tests Configurations

In this study, there are seven design variants that all contain a similar schematic but implement different PCB layout techniques (see [1] for the details). The design variants are described in Table 1.

Table 1: Design variants

Table 2 shows the test configurations used during the testing of the selected variants.

Table 2: Description of test configurations

2. Immunity Testing Results – Configuration A

Variant 1 and Variant 2 test results are shown in Figure 2.

Figure 2: Configuration A: Variant 1 vs. Variant 2

Next, Variant 5 was tested, and the results were compared to those of Variant 2. The comparison is shown in Figure 5.

Configuration A: Variant 1 vs. Variant 3

Figure 3: Details of the conductive enclosure

Observations: Variant 5 showed slightly worse performance than Variant 2 across the entire spectrum. This demonstrated that splitting the grounds, ground (GND) and analog ground (AGND), has a negative impact on the performance.

Next, Variant 6 was tested, and the results were compared to those of Variant 5. The comparison is shown in Figure 6.

Figure 4: Configuration A: Variant 2 vs. Variant 4

Observations: Variant 6 performed slightly better than Variant 5 except for the region around 460MHz. This could indicate that having AGND isolated on Layer 3 has a positive impact on the performance in a split ground topology.

Figure 5: Configuration A: Variant 2 vs. Variant 5

Next, Variant 7 was tested, and the results were compared to those of Variant 6. The comparison is shown in Figure 7.

Figure 6: Configuration A: Variant 5 vs. Variant 6

Figure 7: Configuration A: Variant 6 vs. Variant 7

Observations: Jumping the analog traces from Layer 1 to 3 (Variant 7) introduces regions where one variant outperforms the other. Variant 7 shows better immunity in the lower frequency range, while Variant 6 is better in the mid-frequency range. Our experience has shown that jumping layers should be avoided as it introduces anomalies in an unpredicTable frequency range.

3. Immunity Testing Results – Configuration B

The three variants which exhibited the weakest RF immunity performance in Configuration A were re-tested in the same frequency range. The weakest RF immunity was exhibited by Variants 1, 5, and 6.

Figure 8 on page 44 compares the test results for Variant 1, Configuration A vs. B.

Figure 8: Variant 1 – Configuration A vs. B

Observations: Variant 1 in Configuration A generally outperforms Configuration B up to 700MHz. Between 700MHz and 800MHz, Configuration B shows a benefit. Beyond 800MHz, there is no noticeable difference in performance. Based on the data, an ungrounded shielded enclosure provides benefits in a limited frequency range.

Figure 9 on page 44 compares the test results for Variant 5, Configuration A vs. B.

Figure 9: Variant 5 – Configuration A vs. B

Observations: Variant 5 in Configuration B performed similarly to Configuration A with the exception of 400MHz and 740MHz – 880MHz range. There are inconsistent benefits of Configuration B most likely due to the split ground strategy that doesn’t provide complete shielding from the enclosure.

Figure 10 on page 44 compares the test results for Variant 6, Configuration A vs. B.

Figure 10: Variant 6 – Configuration A vs. B

Observations: Variant 6 in Configuration B performed similarly to Configuration A with the exception of frequencies around 420MHz and 620MHz – 720MHz range. There are inconsistent benefits of introducing an ungrounded conductive enclosure (Configuration B). In Variant 6, the analog traces are routed on the top layer with PCB GND surround and a separate Analog GND beneath on Layer 2. All other layers are PCB GND. These layout design features make the ungrounded shielded enclosure have less impact on the immunity performance.

4. Immunity Testing Results – Configuration C

Finally, the worst-performing variant from Configuration B (Variant 1) was re-tested in the same frequency range. Figure 11 compares the test results for Variant 1, Configuration A vs. C.

Observations: Variant 1 in Configuration C performed dramatically better than Configuration A over a wide band of frequencies from 400MHz to 1000MHz. Improvements were made due to the shielded enclosure, conductive standoffs, conductive gaskets, and selective filtering components on the analog lines. Since Configuration B (shielded enclosure, non-conductive standoffs) didn’t provide as much benefit as Configuration C, the added conductive gaskets, conductive standoffs, and component filtering likely provided the most benefit.

Figure 11: Variant 1 – Configuration A vs. C

5. Future Work

The next article will discuss the results of the RF conducted immunity testing.

References

Baatar, B., Costantino, C., Morey, R., Muldowney, C., EMC PCB Design Study, GVSU senior project sponsored by E3 Compliance, LLC.
Adamczyk, B., Mee, S., Baatar, B., “Evaluation of PCB Design Options using a Multilayer PCB – Part 1: Top-Level Description of the Design Problem,” In Compliance Magazine, May 2022.

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Dr. Bogdan Adamczyk is professor and director of the EMC Center at Grand Valley State University (http://www.gvsu.edu/emccenter) where he regularly teaches EMC certificate courses for industry. He is an iNARTE certified EMC Master Design Engineer. Prof. Adamczyk is the author of the textbook “Foundations of Electromagnetic Compatibility with Practical Applications” (Wiley, 2017) and the upcoming textbook “Principles of Electromagnetic Compatibility with Laboratory Exercises” (Wiley 2022). He can be reached at adamczyb@gvsu.edu.

Scott Mee is a co-founder and owner at E3 Compliance which specializes in EMC & SIPI design, simulation, pre-compliance testing and diagnostics. He has published and presented numerous articles and papers on EMC. He is an iNARTE certified EMC Engineer and Master EMC Design Engineer. Scott participates in the industrial collaboration with GVSU at the EMC Center. He can be reached at scott@e3compliance.com.

Bilguun Baatar is an electrical engineer specializing in EMC design and testing. He graduated from Grand Valley State University with a BSE in Electrical Engineering and his focus is on EMC pre-compliance testing and expanding the understanding of EMC concepts/procedures. He can be reached at bilguun.baatar@e3compliance.com.

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