Under the Medical Device User Fee and Modernization Act (MDUFA) and its successive amendments, the FDA must meet performance goals related to the agency’s review of medical device submissions, based on the timeliness of those reviews. The FDA’s Refuse to Accept (RTA) policy provides for an early review of all submissions in accordance with specific acceptance criteria and enables the agency…

DILBERT © 2022 Scott Adams. Used By permission of ANDREWS MCMEEL SYNDICATION. All rights reserved.

n recent years, we’ve noticed a growing confusion in the industry over design and performance requirements for sensitive compartmented information facilities (SCIF). Part 2 of this article is intended to highlight the significant difference in the performance of radiofrequency (RF) shielding between facilities designed per ICS/ICD-705^[1] and those intended to meet NSA 94-106^[2] performance requirements. We will also highlight some of the design and construction methodologies that lead to significant differences in performance.

oday, military and avionics electronic systems are being developed with increased frequency ranges to add bandwidth and functionality while also being designed to fit smaller spaces. Meeting reduced size, weight, and power (SWaP) system goals poses challenges for high-frequency RF/microwave cables and connectors that must meet complex electrical, mechanical, and environmental specifications but also enable access to subsystem modules for maintenance and troubleshooting. Fortunately, new multiport interconnector technologies exhibit low loss at RF/microwave frequencies with high security and repeatability. Their straightforward approach makes it easy to disconnect even in space-limited applications while maintaining the most demanding EMI/EMC requirements.

Civilian and military avionics systems such as radar altimeters and microwave landing systems (MLS) that once occupied DC to 12 GHz are now expanding into higher frequencies, typically to 18 GHz and often as high as 40 GHz. This expansion requires subsystem interconnects capable of providing the highest, most reliable performance while also fitting within limited airframe space.

ecause virtually all electronic devices and electrical apparatus require safety certification, manufacturers must submit samples of their products to compliance agencies and regulatory authorities to ensure they meet global standards.

This article gives an overview of the many safety standards required for certification and how advanced hipot testers have evolved to speed and simplify the compliance process. It also discusses the critical pre-testing setup and safety procedures required to ensure user safety. Finally, it describes the four types of essential hipot tests, dialectic withstand, insulation resistance, ground continuity, and ground bond testing, conducted during final production as well as the test results to look for.

During the production phase of product development, products destined for sale in the U.S. market are typically sent to Nationally Recognized Testing Laboratories (NRTLs) for compliance testing. NRTLs provide services to certify compliance with the relevant standard(s) and regularly inspect the testing equipment and facilities.

art I of this article focused on the distinction between safety-critical components and high-integrity components. In this second part, we discuss the main aspects related to high-integrity components.

An effective HIC safety strategy views hazard identification and hazard analysis and control as a continuous, iterative process applied throughout HIC development and use. Once hazards have been identified, they are addressed either by eliminating them from the HIC design if possible or, if not, by preventing or minimizing their likelihood of occurrence, controlling the risks that do occur, and minimizing their potential damage. Safety must be built into an HIC from the beginning; it cannot be added to a completed design or tested into an equipment.

his is the second of three articles devoted to the design, test, and EMC immunity evaluation of multilayer PCBs containing analog circuitry. The first article presented a top-level block diagram description of the design problem under research [1,2]. This article is devoted to the RF immunity testing according to the ISO11452-11 Radiated Immunity Reverberation Method standard from 400MHz – 1GHz, up to 100V/m. As a reminder, two analog measurements are present on the PCB. The first analog measurement captures analog temperature values from a Negative Temperature Coefficient (NTC) thermocouple at the end of a short harness. The second analog measurement captures the analog voltage of 12 volts connected at the banana jack terminals of the PCB. Both sets of values are processed by the microcontroller and reported to the test engineer outside the chamber via Universal Asynchronous Receiver Transmitter (UART) and fiber optic communications for isolation. However, for this article, only analog temperature measurements are presented and discussed.

In this study, there are seven design variants that all contain a similar schematic but implement different PCB layout techniques (see [1] for the details). The design variants are described in Table 1.

hen handling ESD-sensitive components, we must protect them from ESD damage. ANSI/ESD S20.20 tells us its purpose is “to provide administrative and technical requirements for establishing, implementing and maintaining an ESD Control Program,” and it “applies to organizations that manufacture, process, assemble, install, package…. or otherwise handle…parts, assemblies, and equipment susceptible to ESD damage…” It all sounds very “big company.”

What if you have three people trying to run a repair shop or make a few products? Or a single servicing engineer visiting customers? Even larger companies sometimes have single workstation electrostatic protected areas (EPA) or activities that do not seem to fit the standard. Not to mention the R&D guys with a single workstation prototyping area… It just does not seem practical to have ESD control according to IEC 61340-5-1 and ANSI/ESD S20.20, and why would they bother?

Let us deal with the last bit first. As an R&D guy, I would not want to waste my time trying to debug a prototype that I had unknowingly damaged through ESD. I would want this even less if my project was a one-off product going to a customer or if I was fitting memory or boards into a client’s equipment. Yes, it does happen.