Voltage to Current Correlation for CDM Testing

hot topics in ESD

By Lena Zeitlhoefler, Theresa Lutz, Friedrich zur Nieden, Kai Esmark, and Reinhold Gärtner for EOS/ESD Association, Inc.

New Approaches for CDM Testing

It is now well known that testing for CDM ESD evaluation is becoming a bigger challenge. Previously, (In Compliance Magazine, March 2021) Capacitively Coupled TLP (CCTLP) was described as an alternate approach. It offers many advantages compared to the standardized field-induced CDM setup according to the JS002 standard [1]. Testing of a package, bare die, or wafer is enabled with high reproducibility. The failure correlation between CDM and CCTLP has been investigated based on peak current stress levels and not by a charging voltage level [2]. If testing with an alternative CDM method as CCTLP is done to reproduce JS002, the CDM charging voltage must be transferred into peak current levels.

Device and Tester Capacitance

A measure for the severity of the CDM stress is the effective capacitance C_eff of a device [3]. C_eff characterizes the amount of exchanged charge between DUT and test setup at a specific stress level (e.g., V_CDM) in a specific testing environment.

Products can be categorized with respect to C_eff in an FICDM setup because of the direct relation to the peak current for a given test voltage, as described in [4].

chart of three-capacitances-model of the CDM tester

Figure 1: Three-capacitances-model of the CDM tester

chart showing coin diameter in mm, height of coin: 1.27 mm

Table 1: Coin diameter in mm, height of coin: 1.27 mm

During a CDM stress, different capacitance values play a role according to the three-capacitances model, as shown in Figure 1.

The three capacitance values determine the effective capacitance C_eff. The DUT capacitance C_DUT is defined as the capacitance from the device to the field plane. The static capacitance value for C_DUT is extracted from a Finite Element Method (FEM) simulation according to the three-capacitances model shown in Figure 1. Differences between C_eff and C_DUT capacitances either extracted from FEM-simulation or calculated as parallel plate capacitance C_plate (A is the area of the DUT, and d is the thickness of the FR4 dielectric layer) are demonstrated based on the metallic circular coin modules (height 1.27 mm, diameters see Table 1).

The FEM simulation of C_DUT does not coincide with the simple plate capacitor formula since fringing effects are also considered, especially for small devices. C_DUT also shows a linear dependency on the area-capacitance relation. In contrast, C_eff values show saturation with increasing area or volume of a DUT. As a result, not only the area of the bottom surface contributes to the capacitance but also the sidewalls and, therefore, the volume.

Impact of Device Dimensions

To calculate the CDM discharge current from the volume, the device area is considered as the maximum edge length a x b, including the pins and mold compound (Figure 3). For a bare die product that does not go into a final package, the area is calculated from the edge length of the silicon accordingly.

Statistical analysis of CDM testing data shows the relevance of device area and volume for predicting stress current levels in a CDM test since the height h of the device has a non-neglectable influence on the discharge current. A database with over 15 million CDM waveforms has been used to evaluate the relation between area, volume, peak current, and the effective capacitance C_eff. The area and volume of about 10000 different device types can be derived from the package dimensions included in the database. For each device type, only the waveforms are evaluated, showing the maximum positive peak current I_peak out of several CDM discharges for a positive charging voltage level of 500 V. According to the measurement results, the peak current reduces with the increasing height of the device.

chart showing correlation between capacitance and area

Figure 2: C_eff, C_DUT, and C_plate related to the area of coins

Figure 3: Definition of device area A = a x b and volume V = A x h

This can be shown using the set of nine cylindrical solid metal coins P1 to P8 with different diameters and volumes (see Table 1)[5]. The coin reference for the peak current still gives a reasonable orientation for the maximum peak current. Figure 4 shows the dependency of the effective capacitance C_eff on the volume. For very flat packages, the limit of the coins is exceeded but still gives a meaningful value. The coin with the smallest volume and, therefore, lowest C_eff reaches the lowest peak current and vice versa. For devices, this means that their C_eff with the according current can be related to the current of the coins. As shown, the device height is becoming relevant for the estimation of the stress current level, therefore, the volume is introduced as the preferred parameter. Thus, the volume value can be used to estimate the expectable peak current with respect to the coin values as shown in Figure 5.

Conclusion

A practical solution is presented for the problem, how CDM targets can be translated to current test levels. CDM current test levels are important as they allow using alternative CDM testing methods, such as CCTLP. The first testing proposal is a simple approach, representing the worst case: Increase the CCTLP testing voltage until the peak current value is reached at the product pin given in Figure 5.

To avoid over-testing, these levels can be lowered based on the second proposal if details of the electrical properties on-package and on-chip are known. C_eff values can be predicted by FEM simulation even before devices are available.

The full paper was published in [6].

chart showing effective capacitance vs. device volume

Figure 4: Effective capacitance vs. device volume for h > 1.27mm. The influence of the device height on the effective capacitance is illustrated per color.

Figure 5: Current vs. volume with illustrated dependency on height.

References

ANSI/JEDEC/ESDA, “Joint Standard for Electrostatic Discharge Sensitivity Testing – Charged Device Model,” JS‑002, 2018
K. Esmark, R. Gaertner, S. Seidl, F. zur Nieden, H. Wolf and H. Gieser, “Using CC-TLP to get a CDM robustness value,” 2015 37th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Reno, NV, USA, 2015, pp. 1-10.
B. C. Atwood, Y. Zhou, D. Clarke and T. Weyl, “Effect of large device capacitance on FICDM peak current,” 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), Anaheim, CA, USA, 2007, pp. 5A.1‑1‑5A.1-10.
N. Jack, B. Carn and J. Morris, “Toward Standardization of Low Impedance Contact CDM,” 2019 41st Annual EOS/ESD Symposium (EOS/ESD), Riverside, CA, USA, 2019, pp. 1-7.
T. J. Maloney and N. Jack, “CDM Tester Properties as Deduced From Waveforms,” in IEEE Transactions on Device and Materials Reliability, vol. 14, no. 3, pp. 792-800, Sept. 2014, doi: 10.1109/TDMR.2014.2316177
L. Zeitlhoefler, T. Lutz, F. Zur Nieden, K. Esmark, and R. Gaertner, “Voltage to Current Correlation for CDM Testing,” 2023 45th Annual EOS/ESD Symposium (EOS/ESD), Riverside, CA, USA, 2023, pp. 1-11, doi: 10.23919/EOS/ESD58195.2023.10287735

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Lena Zeitlhoefler received her master’s degree in Electrical Engineering from the Technical University of Munich in 2017. Her studies included the physics of CDM and CDM simulation and is now on the ESD team at Infineon Technologies.

Theresa Lutz received her Ph.D. from the EPFL in Switzerland in 2011 She works for Infineon Technologies as a development engineer for automotive sensor systems, focusing mainly on ESD and MEMS simulation and modeling.

Friedrich zur Nieden received a Ph.D. degree in Electrical Engineering from the TU Dortmund University in 2014. At Infineon Technologies, he works on ESD characterization, device testing, system-level ESD, and production support.

Kai Esmark has more than 20 years experience in the field of ESD and EOS. He is Senior Principal for “Overvoltage Robust Design” in the Automotive business group of Infineon Technologies in Munich

Reinhold Gärtner received his diploma in physics from the Technical University of Munich in 1987. After working as an independent ESD consultant, he joined Siemens Semiconductors in 1996, now Infineon Technologies.

Founded in 1982, EOS/ESD Association, Inc. is a not for profit, professional organization, dedicated to education and furthering the technology Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, tutorials, and foster the exchange of technical information among its members and others.

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