Impact of PCB Via and Trace Geometry on the Effectiveness of Decoupling Capacitors

EMC Concepts Explained

Part 3: Conducted Emissions Results – Impact of the Distance from Internal Power-Ground Plane Pair and Impact of the Via Topology

By Bogdan Adamczyk, Allyson Telck, and Scott Mee

his is the third and final article in the series investigating the effectiveness of decoupling capacitors while varying the topology of vias, trace length between the decoupling capacitor and the IC power/ground pins, and distance from the internal power-ground plane pair. The first article [1] introduced the electrical schematic, via and trace topologies, as well as PCB topology. The second article [2] addressed the impact of the distance of the capacitor from the IC VCC and GND pins on the conducted emissions. This article investigates the impact of conducted emissions due to the distance of the capacitor from the internal power-ground plane pair and the impact of the capacitor via topology. The conducted emissions are measured using the CISPR25 standard, as shown in the second article [2] in the series.

System Description

Figure 1 shows the block diagram of the system studied. When power is applied to the IC, it toggles the LEDs on and off, rapidly using a constant rate. The purpose of switching the LEDs on and off rapidly is to create a periodic power (charge) draw, thus creating a need for proper Power Delivery Network (PDN) decoupling to reduce or eliminate conducted and radiated emissions. The topology and impact of the decoupling capacitors was presented in [2].

Figure 1: System block diagram

The 6-layer PCB used in our study is shown in Figure 2.

Figure 2: Topology of the 6-layer PCB

Figure 3 shows the capacitor placement on the top and bottom layers.

Figure 3: Capacitor placement on top and bottom layers

One bank of capacitor pads (C1 through C7) is located on the top layer of the PCB, and the other bank of capacitor pads (C8 through C14) is placed on the bottom layer of the PCB, at the same distances from the microprocessor (see [1] for more details). Only one pad at a time was populated with a capacitor having a value of 0.1uF with X7R dielectric.

Six PCBs were tested, each with a different via topology, as shown in Figure 4.

Figure 4: Via topologies

Board 1 had four vias connected to the capacitor. Two vias connect to the board’s internal power plane on layer 3 and were placed on either side of the capacitor’s power pin, approximately 0.03 inches away from the center of the pin pad. The other two connect to the board’s internal ground plane on layer 2 and were placed on either side of the capacitor’s ground pin at the same distance. 0.03 inches separated each power and ground via pair. Straight traces connected the vias to the capacitor.

Board 2 was similar to Board 1 but had only two vias connected to the capacitor instead of four. The via connected to the internal power plane on layer 3 was placed 0.03 inches above the capacitor’s power pin, while the via connected to the internal ground plane on layer 2 was placed 0.03 inches above the capacitor’s ground pin. Again, there was 0.03 inches of separation between the power via and the ground via.

Board 3 had two vias connected to the capacitor, where one was approximately 0.026 inches to the left of the capacitor’s ground pin, and the other was 0.025 inches to the right of the capacitor’s power pin. 0.085 inches separated the vias from each other and connected to their respective internal planes on layers 2 and 3.

Board 4 used only one via, which connected to the board’s internal ground plane on layer 2 and was placed approximately 0.026 inches away from the center of the capacitor’s ground pin. A long trace ran from the capacitor’s power pin to the IC’s power pin.

Board 5 had four vias connected to the capacitor. Each via was placed at a vertical distance of approximately 0.015 inches and a horizontal distance of approximately 0.026 inches from the center of the respective capacitor pin. This left 0.086 inches of distance between each power and ground via pair and connected to their respective internal planes on layers 3 and 2. The traces connecting the vias to the capacitor pin pads were also curved.

Board 6 was similar to Board 3 but had a longer trace between each via and the capacitor. Each via was approximately 0.1 inches from the center of its respective capacitor pin pad and connected to its respective internal planes on layers 2 and 3, making the distance between the vias 0.234 inches.

Conducted Emission Measurement Setup

The measurement setup according to CISPR 25 specification is shown in Figure 5.

Figure 5: Measurement setup for conducted emissions

The RF Conducted Emissions of the PCB assemblies were measured on the external Power and Ground lines using the CISPR25 (CE Voltage Method) standard setup with two Line Impedance Stabilization Networks (LISN). To reduce the number of figures shown, the plots shown are for either the BAT (Battery) or the GND (Ground) line.

Measurements in the frequency range 0.15 – 30 MHz were performed with 9 kHz resolution bandwidth (RBW), while the range 30 – 108 MHz used 120 kHz RBW. Emissions were evaluated against Class 5 limits using the peak, average, and quasi-peak detectors. For clarity, the results for the peak detector are shown in this study.

Conducted Emission Results – Effect of the Distance from the Internal Power-Ground Plane Pair

The distance between a decoupling capacitor and a power-ground plane pair impacted the emissions. This was best seen by comparing the results from Boards 3 and 6 in the 30 – 67 MHz frequency range. Figure 6a shows the results for Board 3 with the capacitor placed near the IC (C1 and C8). The C1 location corresponds to the capacitor placed on the top layer, closer to the power-ground plane pair. The C8 location corresponds to the capacitor placed on the bottom layer, farther away from the power-ground plane pair. Thus, the C1 location creates a smaller current loop during switching than the C8 location. Therefore, we would expect the emissions from the C1 loop to be smaller than those from the C8 loop. This indeed is the case, as Figure 6a shows the difference in emissions steadily increasing in the frequency range 30 – 67 MHz.

Figure 6b shows the results for Board 6 with the capacitor placed furthest away from the IC (C7 and C14). The C7 location corresponds to the capacitor placed on the top layer close to the power-ground plane pair. The C14 location corresponds to the capacitor placed on the bottom layer, further away from the power-ground plane pair. Thus, the C8 location creates a smaller current loop during switching than the C14 location. Therefore, we would expect the emissions from the C8 loop to be smaller than those from the C14 loop. This indeed is the case, as Figure 6b shows, in the frequency range 30 – 40 MHz.

Figure 6: GND line: a) Board 3 – C1 vs. C8 location, b) Board 6 – C7 vs.C14 location

Conducted Emission Results – Effect of the Via Topology

The greatest difference in emissions due to different via topology was observed when comparing Board 3 with Board 6, Board 1 with Board 2, and Board 1 with Board 5. All measurements shown in this study were taken with a peak detector, and the capacitor was only placed at the C1 location to help control the number of variables.

Board 3 vs. Board 6

Board 3 had one via on either side of the capacitor, each approximately 25 mils from the center of the capacitor’s respective power and ground pads. Board 6 had a similar configuration but with the vias placed approximately 100 mils from the center of the capacitor’s power and ground pads, resulting in a longer trace (see Figure 4).

Figure 7a shows that the BAT line emissions of both boards are somewhat similar up to 15 MHz. Beyond that frequency, emissions from Board 6 become higher than emissions from Board 3, with the difference of about 15 dB at the upper frequency of 30 MHz.

Figure 7b shows the GND line results for Board 3 versus Board 6 in the frequency range 30 – 108 MHz. In the range 30 – 53 MHz, Board 6’s emissions are higher with the maximum difference of about 25 dB at 42 MHz. Past the frequency of about 55 MHz, Board 3’s emissions are higher, with the maximum difference of about 17 dB at 67 MHz. As one would expect, since via spacing in Board 6 is larger than via spacing in Board 3, the emissions at higher frequencies increase.

Figure 7: Board 3 vs. Board 6: a) BAT, 0.15 – 30 MHz, b) GND 30 – 108 MHZ

Board 1 vs. Board 2

Board 1 had four vias with two each above and below the capacitor, while Board 2 had only two vias above the capacitor (see Figure 4).

Figure 8 shows the GND line results for Board 1 versus Board 2 in the frequency range 30 – 108 MHz.

Figure 8: Board 1 vs. Board 2 – C1 location – GND line

In the range 30 – 83 MHz, Board 2’s emissions are higher with the maximum difference of about 2 dB at 73 MHz. Past the frequency of about 83 MHz Board’s 1 emissions are about 4 dB higher. As one would expect, doubling the via count helps reduce the inductance (since the inductances are in parallel) and thus reduces conducted emissions.

Board 1 vs. Board 5

Board 5 had four vias similar to Board 1, but the vias were placed on the left and right sides of the capacitor with curved traces, instead of above and below the capacitor with straight traces (see Figure 4).
Figure 9 shows the GND line results for Board 1 versus Board 5 in the frequency range 30 – 108 MHz.

Figure 9: Board 1 vs. Board 5 – C1 location – GND line

In the range 30 – 78 MHz, Board 5’s emissions are higher with the maximum difference of about 12 dB at 68 MHz. Past the frequency of about 78 MHz, Board 1’s emissions are about 6 dB higher. As one would expect, when the PWR and GND vias are separated further, as in Board 5, this results in a higher inductance and thus an increase in conducted emissions.

The best results were obtained by placing 2 vias per pad, locating the vias with close spacing, and placing the capacitor on the side of the board that is closest to the internal power and ground plane pair in the PCB structure. This last aspect is true when the embedded capacitor layers are closely spaced. In this study, the spacing used between the PWR and GND plane pair was 3.9 mils. As this spacing increases beyond 8-10 mils, the embedded capacitance exhibits a higher inductance, making the plane pair less effective for decoupling. These conclusions are consistent with the extensive studies described in [3] and [4].

The authors attempted to extend this study by also measuring radiated emissions. However, due to the limited technology, speed, and current draw of the selected microcontroller and loads, the results showed insufficient radiated noise to draw meaningful conclusions. Therefore, this is the third and final article on the subject.

References

Bogdan Adamczyk, Allyson Telck, and Scott Mee, “Impact of PCB Via and Trace Geometry on the Effectiveness of Decoupling Capacitors – Part 1: Board Topologies and the PCB Circuitry,” In Compliance Magazine, February 2026.
Bogdan Adamczyk, Allyson Telck, and Scott Mee, “Impact of PCB Via and Trace Geometry on the Effectiveness of Decoupling Capacitors – Part 2: Conducted Emissions Results – Impact of the Distance between the capacitor and IC,” In Compliance Magazine, March 2026.
T. Hubing, “Effective strategies for choosing and locating printed circuit board decoupling capacitors,” 2005 International Symposium on Electromagnetic Compatibility, Chicago, IL, USA, 2005, pp. 632-637.
Juan Chen, Minjia Xu, T. H. Hubing, J. L. Drewniak, T. P. Van Doren, and R. E. DuBroff, “Experimental evaluation of power bus decoupling on a 4-layer printed circuit board,” IEEE International Symposium on Electromagnetic Compatibility. Symposium Record (Cat. No.00CH37016), Washington, DC, USA, 2000, pp. 335-338 vol. 1.

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The Authors
Dr. Bogdan Adamczyk is professor and director of the EMC Center at Grand Valley State University where he performs EMC educational research and regularly teaches EM/EMC courses and EMC certificate courses for industry. He is an iNARTE-certified EMC Master Design Engineer. He is the author of two textbooks, “Foundations of Electromagnetic Compatibility with Practical Applications” (Wiley, 2017) and “Principles of Electromagnetic Compatibility: Laboratory Exercises and Lectures” (Wiley, 2024). He has been writing “EMC Concepts Explained” monthly since January 2017. He can be reached at adamczyb@gvsu.edu.

Allyson Telck is participating in a combined degree program to earn a Bachelor of Science in Electrical Engineering and a Master of Science in Biomedical Engineering at Grand Valley State University. She recently completed her final rotation as an Electromagnetic Compatibility Engineering co‑op student at E3 Compliance, which specializes in EMC and high-speed design, pre‑compliance testing, and diagnostics. She can be reached at allyson.telck@e3compliance.com.

Scott Mee is a co-founder and owner at E3 Compliance, which specializes in EMC & SIPI design, simulation, pre-compliance testing, and diagnostics. He has published and presented numerous articles and papers on EMC. He is an iNARTE certified EMC Engineer and Master EMC Design Engineer. Mee participates in the industrial collaboration with GVSU at the EMC Center. He can be reached at scott.mee@e3compliance.com.

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