EMC concepts explained
Evaluation of EMC Emissions and Ground Techniques on 1- and 2-layer PCBs with Power Converters
Part 6: PCB Layout Considerations
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n this article, we discuss the PCB layout considerations and the design of the reference return paths for the one- and two-layer boards.
1. Introduction
The PCB layout and the design of reference return connections (may also be referred to as grounding) play a critical role in the EMC performance of any circuit. This is especially critical for power converters, which are the focus of this series of articles. In circuit design, it can be easy to focus on power and signal trace connections while overlooking or not focusing enough attention on how circuit current returns. Proper reference return design can especially be challenging in single- and two-layer designs where best practices can’t always be applied. It is important to understand and visualize the path of the return current so its entire loop area can be controlled by design. The complete loop area of each circuit tends to be the dominant factor when compared with other parasitic inductances associated with the components or vias. This inductance has a detrimental effect on the EMC performance.
Visualizing the loop areas allows the designer to identify ways to reduce the size and cross-sectional area of the loops, thus reducing the inductance and high-frequency impedance. In single-layer PCB designs, there is fierce competition for copper routing real estate as all routes need to be completed on a single layer. In this setting, we don’t have the luxury of a reference return on the secondary side of the PCB. We rely on prioritizing the reference return connections between critical points and loop areas are often much larger than we would like to see. This can drive the need for additional decoupling capacitors, filter components and ‘jumper’ components to ‘stitch’ reference returns back together across other trace routes. Figure 1 shows an example of a jumper used to ‘stitch’ the ground areas back together across a signal trace route.
Figure 1: Example of GND stitching with jumper
In two-layer PCBs, there is more opportunity for proper reference return design as the additional layer of copper combined with return vias allows us to make a more consistent return path with smaller loop areas. Stitching ground areas together in single- and two-layer PCBs is important not only for better emissions performance but also aids in reducing immunity issues. Figure 2 shows an example of implementing vias connecting different ‘ground floods’ on the top and bottom layers to create a ‘ground mesh’ and improve the flow of return currents. Efforts should be made to reduce the number of signals on the secondary side to create a more solid reference return plane.
Figure 2: Two-layer example of ground connection
Device application notes can sometimes recommend introducing splits into reference returns for returns such as analog and digital circuits. There may be legitimate reasons for splitting the reference returns but in our experience, this almost always causes an increase in EMC emissions or immunity performance issues. When splits are introduced, efforts are required to ‘reconnect’ these separate shapes either with jumpers or with capacitors. Often the efforts to reconnect the separate shapes are not as effective as making the original solid connections in the PCB layout.
2. Visualizing Complete Forward and Return Paths
In the design process, we recommend drawing the forward and return currents of all power and signal paths as a three-step process. Step 1: draw these complete paths (loops) on the electrical schematic itself. Step 2: draw these complete paths (loops) on the PCB board layout. Step 3: minimize the loop areas (and discontinuities) in the PCB layout.
During the design of the DC-DC Buck converter that has been discussed over the last three articles [x], the reference path design has been the main concern and will continue to be a concern of this study. The schematic and layout of this DC-DC Buck converter are shown in Figure 3. Figure 3a shows the power and signal traces as well as the reference return conductors (highlighted in green). Figure 3b shows the corresponding layout traces and the ground pads (highlighted in green).
Figure 3: DC-DC Converter – a) schematic b) layout
All of the power and signal traces were routed on the top layer, and the reference return paths reside on the bottom layer which is a full solid plane. Implementing this circuit (power and signal traces) on the top layer serves two purposes. First, in later parts of this study this circuit will need to be constructed on a 1-layer PCB, and routing it on just the top layer now will help to keep the layouts similar between this PCB and the future one. Second, the full reference plane on layer two provides an ideal return path as it is not constrained. Such an unconstrained path is highly desirable, especially for the high-frequency currents. Without the solid reference plane, the effectiveness of the filtering on the board would be diminished and the loop areas involving the reference return would increase.
Let’s demonstrate this by looking at one of the output filtering capacitors shown in Figure 4. The forward path of the current is A-B-C-D, and the current return path is E-F-G.
Figure 4: Output filtering section of PCB
Currents return to the source following the path of least impedance [x], at DC and low frequencies (below 100kHz or so) this is predominantly the path of least resistance. At higher frequencies, the return predominantly is the path of least inductance. This inductance is the inductance of the loop formed by the currents’ forward and return paths. At the higher frequencies that we are concerned with in EMC, the loop inductance will be the dominating factor in the impedance, meaning the current will likely follow the path of least inductance to return to the source. This loop inductance is kept at a minimum when the return path is directly under the forward path. This means in a completely unbroken ground plane the current will likely flow directly under the forward path as depicted in Figure 4.
With a completely solid GND plane, the currents will have no issues returning directly under the forward path, but in many practical designs this is just not possible. Generally, at least a couple of traces may need to be routed in the GND plane, especially on a two-layer board. The output section of this DC-DC power supply was modified to allow us to analyze how the current might return to the source when the ideal return path is broken by a trace in the GND plane. This modified output section is shown in Figure 5 on page 44.
Figure 5: Modified output DC-DC converter
In this modified case, the feedback was routed on layer two as opposed to layer one. In this case, it would be expected that the current will initially follow the same path as it did in our original layout until it reaches the feedback trace that is routed in layer two. At this point, the current will have to go around the break in the ground plane and continue to return under the forward path back to the source. The loop area added to the currents path introduced by the cut-out in the return plane increases the inductance of the loop. This causes an increase in the radiation from the current loop [1]. Having a cut-out in the reference plane is therefore not desirable in more complicated designs where space is more a premium, this might be unavoidable.
Next, let’s look at the input filtering section shown in Figure 6 on page 45.
Figure 6: Input filtering section of buck regulator PCB
As described in Section 1, the high-frequency current paths were traced. Because we are concerned with the high-frequency noise that is generated by the switching in U1, we assume the current path starts at the Vin of U1. However, in this case, there are multiple possible return paths for the high-frequency currents. The obvious and most likely three paths are through C7, C8, or C9, which are drawn in purple, green, and blue, respectively. To complicate things further, the loop that noise chooses to satisfy may also change with frequency. For example, noise at 100MHz may choose to go through the smaller capacitor, C9, and noise at a lower frequency, such as 500kHz, may choose to go through one of the larger capacitors, C7 or C8. Interrupting any of these return paths has the potential to generate a common mode noise due to increasing the size of the possible current loops if that current path is being used. It is not guaranteed that if one of these paths is interrupted there will be an emissions failure, but it becomes more likely.
As the circuit complexity increases, it becomes challenging to visualize all possible high-frequency current paths. What can be done then?
This is where the application of some good EMC rules of thumb can help. Here are several that we have identified over the years by working on power converters and solving EMC emissions issues:
- Wherever possible, keep a solid reference plane on the secondary (or adjacent) layer
- Place decoupling and by-pass capacitors as close to the IC pins as possible
- Ensure short connections and provide adequate reference via connections adjacent to component reference (GND) pins to ensure a low impedance path (smallest loop area)
- Place all high di/dt components on the same layer of the PCB and in close proximity
- Place optional snubber components (series R C) across the internal switch and free-wheeling diode. Locate components in close proximity with short connections.
- Fill with reference area fill beneath switching components (ICs, inductors, etc.)
All of these approaches reduce the current loop area and serve to reduce radiated and conducted emissions from the switched-mode power supply.
3. Return-Plane Split in AC-DC Converter
The next several articles will be focused on an AC/DC power supply that utilizes an Off-line Flyback circuit. For safety purposes, the primary side and secondary side circuits must be isolated. Figure 7 shows a part of the schematic for the Maxim MAX5022 Evaluation kit [2], with the current path on the primary side of the transformer shown on the left-hand side of Figure 7 whereas the path of the current flow on the secondary side of the transformer is shown on the right side of Figure 7. Forward currents in both loops are drawn in RED color and return currents are drawn in GREEN color. Note the dashed line in parallel with C7 that denotes the current flowing back to the source from the secondary to the primary through a stitching capacitor that is safety rated. This capacitor provides a pre-determined path for the noise currents to return back to their source along the PCB surface rather than through the air, thus reducing radiated and conducted emissions.
Figure 7: MAX5022 EV kit schematic
The capacitor C7 stitches the two grounds together at high frequencies. Next, the return current flows through the current sense resistor (R7) back to the switching transistor completing the loop. The placement of the stitching capacitor impacts the size of the current loop, and therefore it should be placed as close to the transformer as possible. In some cases, a second stitching capacitor is needed so that a stitching capacitor can be provided above and below the body of the transformer. Total values of stitching capacitors must meet the required limitations imposed by isolation requirements.
Future work
The next article will discuss the design of the AC/DC Off-Line Flyback Converter. We will present a schematic and PCB layout along with supporting design documentation.
References
- Adamczyk, B., “Alternative Paths of the Return Current,” In Compliance Magazine, May 2017.
- MAX5022 Evaluation Kit, MAX5022, Rev 3, Maxim Integrated, 2021, https://datasheets.maximintegrated.com/en/ds/MAX5022EVKIT.pdf.
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Dr. Bogdan Adamczyk is professor and director of the EMC Center at Grand Valley State University (http://www.gvsu.edu/emccenter) where he regularly teaches EMC certificate courses for industry. He is an iNARTE certified EMC Master Design Engineer. Prof. Adamczyk is the author of the textbook “Foundations of Electromagnetic Compatibility with Practical Applications” (Wiley, 2017) and the upcoming textbook “Principles of Electromagnetic Compatibility with Laboratory Exercises” (Wiley 2022). He can be reached at adamczyb@gvsu.edu.
Scott Mee is a co-founder and owner at E3 Compliance which specializes in EMC & SIPI design, simulation, pre-compliance testing and diagnostics. He has published and presented numerous articles and papers on EMC. He is an iNARTE certified EMC Engineer and Master EMC Design Engineer. Scott participates in the industrial collaboration with GVSU at the EMC Center. He can be reached at scott@e3compliance.com.
Nick Koeller is an EMC Engineer at E3 Compliance which specializes in EMC & SIPI design, simulation, pre-compliance testing and diagnostics. He received his B.S.E in Electrical Engineering from Grand Valley State University and is currently pursuing his M.S.E in Electrical and Computer Engineering at GVSU. Nick participates in the industrial collaboration with GVSU at the EMC Center. He can be reached at nick@e3compliance.com.