Machine Learning Applications in the Novel ESD Compact Modeling Methodology

hot topics in ESD

MACHINE LEARNING APPLICATIONS IN THE NOVEL ESD COMPACT MODELING METHODOLOGY

By Wei Liang and Ahmed Ginawi for EOS/ESD Association, Inc.

Why IS ESD Compact Modeling Important

Electrostatic Discharge (ESD) is well known as one of the major reliability concerns in semiconductor manufacturing. Proper ESD protection solutions are always required to ensure integrated circuits do not fail during an ESD event. During the IC chip designing process, it is always highly desirable to have a complete set of ESD compact models of ESD protection devices that the IC designer could utilize in circuit-level SPICE simulations to achieve optimized circuit performance. It is important to predict and ensure that the ESD protection circuits and the core circuits are operating as desired, and this is key to achieving the right ESD protection solution for the first time. Therefore, the development of the ESD compact model has become one of the most essential elements in ESD device development.

What is Machine Learning?

Machine learning is a subfield of artificial intelligence (AI) that uses algorithm models to recognize the patterns in each dataset as well as learn and predict based on the supplied training dataset. It consists of a few steps, including data collection, data preparation, training, evaluation, and model tuning. Figure 1 shows the working flow of the generic machine learning concepts. Utilizing machine learning techniques will promote business success by improving time efficiency and design/prediction accuracy. In the semiconductor industry, for example, foundries are trying to apply machine learning techniques to areas like automatic defect classification, electrical tests, acoustic anomaly detection, and predictive equipment maintenance. It can also be used in EDA development, such as simulation models.

Figure 1: Flow chart of generic machine learning concept.

How are Machine Learning Techniques Used in ESD Compact Modeling?

The machine learning technique called Multi-layer Perceptron (MLP) regressor, which is a type of Neural Network model in machine learning, can be used in the new ESD compact model fitting methodology.

In conventional compact model fitting, the modeler fits the model by tuning the parameters of the physical device equations. Figure 2 shows the flow chart of conventional ESD compact modeling fitting. As we mentioned, the fitting step is very time-consuming, and sometimes, the modeler must change the model equations to get the simulated I-V fitted to hardware data and pass the quality check criteria.

Figure 2: Flow chart of conventional ESD compact modeling fitting.

In the new methodology, the fitting process is done by a machine learning model with a behavior-based method instead of manually tuning the parameter of the physical equation. Figure 3 shows the flow chart of the ESD compact modeling fitting using machine learning techniques. The pre-processed raw silicon data and design specification of the structure is divided into three sets, including the training dataset and validation dataset (80% of relevant data), the test dataset (20% of the relevant data), and the new dataset (irrelevant data) which is used to check the model prediction accuracy. Irrelevant data refers to a device perimeter that was never used during the training step and is not relevant to the machine learning process but is needed to check prediction accuracy.

Figure 3: Flow chart of novel ESD compact modeling fitting using machine learning techniques.

What are the Advantages of the New Methodology?

There are two main advantages: efficiency and accuracy.

For efficiency, model development can usually be categorized into three phases: device characterization and data-pre-processing, model fitting, and model quality check. Figure 4 shows the development time comparison between the conventional and novel ESD compact model development. Using the conventional methodology, an 8-week timeline is typically quoted by an experienced ESD device modeler on a new ESD diode model with TLP, vf-TLP, and DC characteristics. As a comparison, to develop the same model using a novel ESD compact modeling methodology, the model fitting step could save up to 62% of the time, which brings the overall development time saving to 31%. More time could be saved if Machine Learning techniques are applied to data processing and quality checks in the future.

Figure 4: Development time comparison between conventional and novel ESD compact modeling methodology.

For accuracy, Figure 5 shows an example of the comparison among hardware, machine learning simulated, and conventional SPICE model simulated results for an ESD diode. Figure 6 shows the comparison between hardware data and machine learning model simulated I-V characteristics with ESD perimeter variation.

Figure 5: 100ns TLP I-V characteristics comparison among hardware, machine learning model, and SPICE model of the ESD diode.

100ns TLP I-V characteristics comparison between hardware and machine learning model simulation with perimeter variation of the ESD diode

Figure 6: 100ns TLP I-V characteristics comparison between hardware and machine learning model simulation with perimeter variation of the ESD diode.

The machine learning model simulated I-V characteristics with at least 10% better accuracy in matching the hardware. The machine learning model not only has better accuracy and runtime efficiency but also shows a better current saturation effect compared to the traditional SPICE model using physical equations.

Overall, the novel machine learning-based ESD model will significantly simplify the development work and improve the model prediction accuracy over the traditional SPICE model. It could also achieve some challenging work that traditional SPICE models are not good at, like fitting for I-V characteristics with snapback behavior. It would bring evolutionary changes to future ESD compact modeling work.

Reference

W. Liang, X. Yang, M. Miao, A. Loiseau, S. Mitra and R. Gauthier, “Novel ESD Compact Modeling Methodology Using Machine Learning Techniques for Snapback and Non-Snapback ESD Devices,” in IEEE Transactions on Device and Materials Reliability, vol. 21, no. 4, pp. 455‑464, December 2021, doi: 10.1109/TDMR.2021.3116599.

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Wei Liang leads ESD and Latchup strategies for Intel AMS IPs. Previously, he worked on the GlobalFoundries ESD team. Wei holds an MBA from Boston University and a Ph.D. in Electrical Engineering from UCF. He has authored more than 20 peer-reviewed papers and holds more than 10 U.S. patents in ESD.

Ahmed Ginawi joined Intel in 2023 as the Senior Director under the Fundamental IP organization, and before that, Ahmed served as the team lead for foundry IO design and foundry ESD at GlobalFoundries and IBM since 2000. Ahmed has several publications and patents in IP design and ESD applications.

Founded in 1982, EOS/ESD Association, Inc. is a not-for-profit, professional organization dedicated to education and furthering the technology of Electrostatic Discharge (ESD) control and prevention. EOS/ESD Association, Inc. sponsors educational programs, develops ESD control and measurement standards, holds international technical symposiums, workshops, and tutorials, and fosters the exchange of technical information among its members and others.

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