Die-to-Die ESD Discharge Current Analysis

Feature Article

closeup of glowing microchip on blue motherboard

Editor’s Note: The paper on which this article is based was originally presented at the 45^th Annual EOS/ESD Symposium in September 2023. It was subsequently awarded the 2024 Symposium Outstanding Paper at the 46^th Annual EOS/ESD Symposium in September 2024. It is reprinted here with the gracious permission of the EOS/ESD Association, Inc.

dvanced system on a chip (SoC) components use multi-die package technologies where single silicon chips are assembled on top of each other, beside each other on a larger interposer, or by combining various 3D packaging methods together. Connections between chips are formed by utilizing multiple technologies such as flip chips, substrates, interposers, silicon bridges, bond wires, micro bumps, and through-silicon-vias (TSV).

A single SoC can have hundreds to thousands of external connections between a component package and a printed circuit board (PCB). These connections require certain robustness against external electrical stress and can often tolerate electrostatic discharge (ESD) withstand voltages of more than 250 V charged board model (CDM) and 500 V human body model (HBM) during qualification tests. Each of these on-chip protection structures requires surface area from the silicon, but due to a limited number of connections, this is still feasible.

There are more die-to-die (D2D) interconnections inside an SoC than between the package and PCB, and it is estimated that the number of interconnections increases with future technologies [1][2]. Most interconnections are well protected after the SoC is assembled and don’t need the same level of ESD robustness as the external interfaces. A certain basic ESD robustness is still required for frontend and backend processes, even though these are made inside a well-controlled cleanroom environment, fulfilling electrostatic protective area (EPA) precautions.

D2D assembly process phase in the backend can have CDM-like ESD risks. Here, bare dies are joined together with an automated handler so that interconnection surfaces directly contact each other. Handlers are well grounded, and ionizers mitigate electrostatic charge buildup. However, it is challenging to control die charging in a fast-paced process where parts contain both dielectrics and conductors. Ionization time is limited, and dies can have charges trapped on opposite surfaces facing trays and pickup nozzles. Ionizers can typically limit charging of large objects below ±10 V, but it is challenging to limit charging of small chips during fast pick and place processes.

There is limited information available about ESD current waveforms from small capacitance sources when the initial potential difference is below 100 V. Several papers discuss discharges between IC packages, and ESD events between dies should have mostly similar initial conditions [3]. Here, the discharge current waveform depends on the initial charge, capacitance, and discharge path. Similarly, the quasistatic ESD source capacitance of the die depends on the size, location, surroundings, and design of the die.

In this study, 3D electromagnetic solvers and circuit calculations are used to study D2D discharge events. Here, the main target is to identify significant discharge parameters affecting ESD current waveforms. The key parameters to study are the contact potential, resistance, rise time, peak current, and length of the pulse. This data is used to estimate reasonable protection targets for D2D interfaces and to give information on how to measure D2D discharge events [4].

Methods

Discharge Current Calculations

ESD current waveform calculations are made in the time domain by using SPICE circuits presented in Figure 1 and Figure 2. Here, the two discrete components R_series and L_series are the parasitic series resistance and inductance of the discharge path. Figure 2 has the same circuit but now with additional discrete components presenting on-chip discharge path termination. This termination can contain on-chip protection structures and transistor input gate parameters, which are simplified here as 50 Ω termination and parasitic LC components. The component F with one or more ports is the calculated frequency response of the 3D discharge setup [5].

Figure 1: Simplified SPICE equivalent circuit for ESD discharge current calculations with one port setup

Figure 2: SPICE equivalent circuit for ESD discharge current calculations with two ports. The first port is the location of the discharge, and the second is used to model on-chip ESD protection circuits.

Figure 3 shows an example of a 3D setup for a μBGA die assembly with one signal port (enlarged for visualization) between the interposer and IC. This port is the discharge contact point between the die and interposer, and can be placed on any of the component joints depending on the discharge scenario under investigation. Both the IC and interposer are made of aluminum. A pick-up nozzle is located above the μBGA and contains grounded conductors, which define part of the source capacitance of the μBGA.

Figure 3: A simplified simulation setup where a pickup nozzle places a μBGA component on an interposer. μBGA has 120 micro bumps with 150 μm pitch. The red rectangle is the excitation port (discharge point) used to calculate the frequency response of the setup.

Figure 4 presents a more complex scenario, in which a μBGA is assembled on top of a 28 mm x 28 mm size IC using a nozzle. The discharge path is marked with red color, and an arrow indicates the discharge location. Ports are placed at the discharge point and at the bondwire contact point on the surface of the die. In this way, we can calculate discharge currents and voltages at both locations by using the circuit of Figure 2.

Figure 4: 3D assembly scenario where 7 mm x 7 mm size μBGA is assembled on top of a larger 28x28 mm size IC. Both components have a leadframe, bondwires, and joints under the package.

Figure 4: 3D assembly scenario where 7 mm x 7 mm size μBGA is assembled on top of a larger 28×28 mm size IC. Both components have a leadframe, bondwires, and joints under the package.

There can be multiple ports in one 3D setup so that different discharge point calculations can be made by using the same 3D model. The model can contain frequency-dependent dielectrics and conductivity based on the used materials.

Bandwidth Requirements

The SPICE circuits in Figure 1 and Figure 2 can calculate discharge current waveforms both by using 3D frequency response data of the 3D model or by replacing the model with a simplified RLC representation of the ESD source circuit. Here, the source ESD capacitance and parasitic inductance are the key parameters when considering the required bandwidth and rise time. These values can be calculated with basic analytical equations or with 3D electromagnetic simulation tools as presented in Figure 5 [3]‒[6]. Here, the die is simplified as an aluminum block placed at varying distances from the reference surface. Unlike RLC circuits or analytic calculations, 3D frequency response models contain a full description of the source model frequency behavior, and these are used in this study. For example, one port 3D model produces S11 response calculated at the port location as shown in Figure 6.

Figure 5: 2 mm x 2 mm x 0.4 mm size charged die 10 μm above the ground plane. An adaptive mesh matrix is visible on the model surface.

Figure 6: An example frequency response of D2D scenario when calculated at the discharge point. Here, the discharge point is the corner of the die with varying die area and distance to the ground reference.

The physical size of dies can vary from a few square millimeters up to >500 mm². ESD risks should decrease with a smaller die size due to a lower source ESD capacitance and stored energy. However, a smaller die can produce faster rise time pulses, and smaller dies can get higher quasi-static voltages with the same amount of charge. With large size dies, the source capacitance increases, thus also increasing the rise time, peak discharge current, and discharge energy, if compared to a small size die with the same initial voltage.

The required bandwidth for a measured or simulated D2D discharge event depends on the materials used, the discharge voltage, and the physical size of the setup. With small dies (a few square millimeters in size) most of the discharge energy is at frequencies above 20 GHz, if external discharge path series parasitics are not included. In this study, the bandwidth is typically calculated for 10 MHz – 100 GHz.

Figure 6 presents an example S11 data for three different discharge scenarios for small-sized dies with 10 μm or 20 μm distance to the ground. This shows that the required calculation and measurement bandwidth should be >25 GHz to capture the rise time and peak discharge current at the contact point.

Inductance and Resistance

The resistance and inductance of the plasma channel change based on the length and width of the channel when discharge voltages are above Paschen limits. However, the die assembly is made in a controlled environment where charge buildup is limited. There is also mutual capacitive coupling between electrically floating charged objects, decreasing the discharge voltage before a physical contact [12]. Therefore, with voltage differences below tens of volts and a narrow <10 μm range gap between dies, Paschen’s law does not apply [7][8].

The strength of the E-field can be high in small gaps even if the potential difference would be just a few Volts. For example, 1 V potential and 1 μm gap create an E-field of 1 MV/m. An electric field emission in air would require significantly higher field strength to pull electrons free; thus, we can assume high resistance and limited current flow before a physical contact [9][10]. In this case, conductors of the die will most likely discharge only when contacting another surface, and thereby, there is no major additional series inductance at the discharge point due to the spark channel.

There can be significant contact resistance during a low voltage transient event between conductors. Therefore, when a die contacts another conductor, the contact resistance can vary from less than one ohm to some unknown higher value. Some additional variation to the contact resistance comes from possible atmospheric pressure differences, surface oxidation, contact area, roughness of surfaces, contact force, protective gases, moisture, power of the discharge current, and varying temperatures used inside the D2D assembly handling environment [10][11]. A contact resistance is treated as a variable and calculated or estimated from RLC circuit waveforms matching with measured discharge current waveforms [6]. The contact resistance can vary during the discharge, but in this study, the resistance is kept constant in calculations [4].

Results

Simplified Discharge Setup

A simplified discharge scenario based on the circuit shown in Figure 1 and a solid aluminum block source as shown in Figure 5 produces ESD current waveforms presented in Figure 7 at the discharge point when the series resistance is between one ohm and 18 Ω. Here, the size of the “die” is 5 mm × 5 mm × 0.4 mm, a gap to the reference ground is 10 um, series inductance is 50 pH, and the discharge potential is 10 V. The current waveform is underdamped when the resistance is below four ohms and overdamped above this value. The peak current and rise time depend mostly on the series resistance and inductance, and the frequency response of the setup with 25 pF source capacitance. Below 10 Ω the peak current can be a few amps with the used 10 V initial voltage.

Figure 7: Discharge current waveforms from 5 mm x 5 mm size die. The series contact resistance varies between 1 Ω and 18 Ω. 10 V initial potential and the size of the gap is 10 μm.

Figure 8 and Figure 9 have the same setup, but now the physical area of the die is between 4 mm² and 25 mm². The series resistance and inductance are 2 Ω and 5 pH in Figure 8, and 10 Ω and 50 pH in Figure 9. These waveforms can be assumed to be worst-case discharge scenarios due to the relatively low series resistance and inductance. The discharge peak current is between 3 A and 4 A in Figure 8, and it drops below 1 A in Figure 9 due to the higher resistance.

Figure 8: Discharge current waveforms with different-sized dies. R_series=2 Ω, L_series=5 pH, V_pulse=10 V, gap=10 μm

Figure 9: Discharge current waveforms with different-sized dies. R_series=10 Ω, L_series=50 pH, V_pulse=10 V, gap=10 μm

Figure 10 and Figure 11 repeat the same simulations, but now the gap length is 20 μm, and the die size is larger, 56.3 mm² and 100 mm². The rise time increases with larger dies, and the peak current follows the source capacitance.

Figure 10: Discharge current waveforms with different-sized dies. R_series=2 Ω, L_series=5 pH, V_pulse=10 V, gap=20 μm. Die size is 56.3 mm2 and 100 mm2

Figure 10: Discharge current waveforms with different-sized dies. R_series=2 Ω, L_series=5 pH, V_pulse=10 V, gap=20 μm. Die size is 56.3 mm² and 100 mm²

Figure 11: Discharge current waveforms with different-sized dies. R_series=10 Ω, L_series=50 pH, V_pulse=10 V, gap=20 μm. Die size is 56.3 mm2 and 100 mm2

Figure 11: Discharge current waveforms with different-sized dies. R_series=10 Ω, L_series=50 pH, V_pulse=10 V, gap=20 μm. Die size is 56.3 mm² and 100 mm²

Based on these calculations, the series inductance and resistance are sensitive parameters from the discharge peak current and the rise time point of view. The source capacitance charges the length of the pulse, the rise time, and the total energy content. With overdamped current waveforms, the initial rise time of the current can be just tens of picoseconds due to a lower peak value, even if the total period of the pulse would be close to one nanosecond.

Capacitive Coupling and Charge Distribution

The voltage difference at the discharge moment depends on the charge distribution and mutual capacitive coupling between dies [12]. In addition, a die held by a nozzle may not be perfectly parallel to the reference surface. In this case, one edge or corner can contact the reference surface at first, as presented in Figure 12. This changes capacitive coupling, electrostatic charge distribution, and the discharge current waveform at the contact point.

Figure 12: Surface charge density of 4 mm x 4 mm x 0.4 mm size die with 1-degree tilt and 10 μm minimum distance to the ground plane. There is more charge stored at the bottom of the die around the edge closest to the ground plane.

Figures 13 – 15 show the potential of two dies and the potential difference between dies when they approach each other. Dies are modelled with ideal solid aluminum blocks. The smaller 4 mm × 4 mm size die has a constant 100 pC static charge, and the larger 14 mm × 14 mm size die is either grounded or electrically floating. In Figure 13, both dies are in parallel position, in Figure 14, the smaller die is tilted 0.5°, and in Figure 15, it is tilted 1°. Above the smaller die is a grounded nozzle with a 0.2 mm thick dielectric isolation layer touching the die surface, so that mixed charge distribution is part of the calculation.

Figure 13: 4 mm × 4 mm size Die 1 with 100 pC static charge moves close to 14 mm × 14 mm size Die 2. Die 2 is grounded or electrically floating.

Figure 14: Die 1 with 100 pC static charge and 0.5° tilt moves close to Die 2. Die 2 is grounded or electrically floating.

Figure 15: Die 1 with 100 pC static charge and 1° tilt moves close to Die 2. Die 2 is grounded or electrically floating.

When both dies are parallel and the larger die is electrically floating (GND float), the final voltage difference between dies is 1.8 V at 5 μm distance. The voltage difference increases to 3.4 V if the larger die is grounded (GND 0 V). Similarly, with a tilted die, the voltage difference is smaller when both dies are electrically floating. However, a 0.5° tilt angle already increases the voltage difference to 6.9 V and 10.5 V with floating and grounded scenarios in Figure 14. 1° tilt angle increases the voltage difference to 10.4 V and 15.5 V, as shown in Figure 15.

Based on Figures 13 – 15, the expected typical discharge voltage during a D2D ESD event in a controlled environment could be less than about 10 V at 5 μm distance, even if the initial voltage of the die would be >100 V after pickup. However, the real potential values can vary in the die assembly as dies are not ideal solid metal blocks with an even surface at the bottom coupling to the reference surface.

Figure 16 has a calculation where a nozzle with 16 mm² area is holding a 25 mm² size die with solder pumps under the package. This is a similar setup as that presented in Figure 3. In this case, the capacitive coupling effect is weaker due to the different charge distribution. The total static charge of the die is set to 1 nC when it is held by a conducting nozzle and 120 pC when the die is held by a non-conducting ceramic nozzle. The reference surface, an electrically floating interposer, has no charge. With these initial charge values, dies have 270 V initial potential when kept at 0.5 mm distance from the interposer. With the conducting nozzle, the voltage difference is about two times higher when the die touches the interposer. However, this phenomenon depends on the nozzle‑die geometry as presented in Figure 17. Here, the size of the metallic nozzle is fixed to 16 mm², and the size of the die varies. If the size of the nozzle is large in comparison to the area of the die, the capacitive coupling phenomenon is weaker when the die approaches the interposer. Figure 17 also shows results without a nozzle for comparison.

Figure 16: Capacitive coupling in a die assembly with a metallic and ceramic nozzle. The die has micro pumps under the package.

Figure 17: Capacitive coupling in a die assembly with a metallic nozzle and without a nozzle. Die has micro pumps under the package.

As a summary, it would be better to use non-conductive low-capacitance nozzles when assembling dies. In addition, it would be better to let the second die or interposer electrically float to magnify capacitive coupling phenomena during assembly. Also, it would be good to keep the die parallel to the reference surface to magnify capacitive coupling phenomena.

Discharge Current Analysis

Figure 18 has discharge current waveforms between two dies representing the scenarios presented in Figures 13 – 15. In this calculation, the smaller die has a fixed 10 V potential and is tilted 0°, 0.5°, or 1° in comparison to the larger electrically floating die. The peak discharge current is the highest when dies are parallel, and the current decreases with increasing tilt angle due to the smaller source capacitance. However, capacitive coupling is weaker with tilted dies, and this would magnify the voltage difference and change the contact resistance in real‑life discharge scenarios. The final discharge current waveform would be case‑specific, depending on the die construction, contact resistance, and variations with the die alignment.

Figure 18: Discharge current waveform from a 4 mm x 4 mm size die to another electrically floating die. The die is parallel or tilted with a constant 10 μm minimum gap and a fixed 10 V potential between the two dies.

Figure 19 shows the frequency response of the source circuits for the three discharge waveforms presented in Figure 18. Alignment of the die changes the frequency response of the source. Most of the energy is above 10 GHz and the current rise time is about 12 ps, which corresponds to the frequency content around 70 GHz – 80 GHz.

Figure 19: Frequency response of the D2D discharge setup

Discharge current waveforms can vary depending on the location of the contact point. In Figure 20 on page 33, the discharge point is in the middle of the die, at the corner, and at the middle of the edge. Here, the size of the die is 4 mm × 4 mm × 0.4 mm, and the potential difference is 10 V. The highest peak current and fastest rise time occur in the middle of the die, and the corner of the die has the most attenuated discharge current waveform. Similar results have been reported by earlier studies on CDM discharge testing with larger IC packages [13].

Figure 20: Comparison of D2D discharge current waveforms from the middle, corner, and middle of the edge of the die

The series contact resistance is significant from the peak discharge current point of view, as shown in Figure 21. However, it has less effect on the rise time. With overdamped current pulses, the rise time is around 20 ps; even so, the decay time is measured in the nanoseconds regime.

Figure 21: Discharge current waveform from 4 mm × 4 mm size die to the ground plane. With over 10 Ω resistance values, the discharge current waveform is overdamped.

D2D discharge current waveforms can be different with more complex die and interposer constructions if compared, for example, to the waveforms presented in Figure 18 and Figure 20. Figure 22 has discharge current waveforms based on Figure 4 and Figure 2 setup, where both dies or interposers have a leadframe, bondwire structures, micro vias, and μBGA connections. In this case, there is more inductance and parasitic capacitance along the discharge path.

Figure 22: Discharge currents at the die gate input when a charged μBGAs discharges to a larger component. Contact series resistance as a variable.

Figure 22 presents the current at the transistor gate input area with four different contact resistance values. The waveform has two oscillating waveforms. At first, there is an initial fast pulse with about 150 mA peak current amplitude and multiple reflections originating from the leadframe structures close to the discharge point, as shown in Figure 23. This oscillation lasts about 150 ps. The main discharge current pulse with about 80 ps rise time follows from the rest of the structure and has the peak current amplitude of about 300 – 500 mA, depending on the value of the contact resistance.

Figure 23: Initial 150 ps time period of the discharge current waveform shown in Figure 22

As a summary:

We can have both underdamped and overdamped discharge current pulses depending on the series contact resistance.
Due to the low contact inductance, the rise time can be just tens of picoseconds.
With overdamped pulses, the rise time can be around tens of picoseconds, even so the decay time of the current pulse is several nanoseconds.

The rise time increases when the die or interposer has inductive structures, such as bondwires or a leadframe.
Capacitive coupling and non-parallel surfaces affect both the rise time and peak current.
The discharge current waveform can contain multiple waveforms with varying frequency content.

Discharge Current Analysis with Limited Measurement Setups

D2D events do not necessarily resemble typical CDM discharges due to <20 V potential difference, faster current rise time, short pulse, and small total charge transfer. It is also challenging to measure discharge events with a low initial potential level, low source capacitance, and varying contact resistance. More challenges can arise from any additional parasitic series inductance, increasing the rise time. Based on calculations, the required measurement bandwidth can be > 20 GHz; thus, it can be difficult to measure current waveforms without changing the discharge scenario.

Figures 24 and 25 have calculations for discharge events where the series inductance, resistance, and capacitance are variables. Figure 24 has a fixed 5 pF source capacitance, and Figure 25 has a larger 10 pF source. Both figures have three discharge groups where the series inductance is set to 0.1 nH, 1 nH, and 10 nH. With each inductance value, the series resistance is 5 Ω, 15 Ω, 25 Ω, and 35 Ω. From both figures, we can see that the peak current depends more on the series resistance when the series inductance diminishes. Respectively, with larger inductance values, the series resistance has less effect on the peak current. In addition, both the series inductance and source capacitance affect the peak current, but the series resistance is the most sensitive discharge parameter from the peak current point of view, with low inductance D2D discharges.

Figure 24: Calculated discharge current waveforms from 5 pF source with 0.1 nH, 1 nH, and 10 nH series inductance. Series resistance changes with each inductance value from 5 Ω to 35 Ω with 10 Ω steps.

Figure 25: Calculated discharge current waveforms from 10 pF source with 0.1 nH, 1 nH, and 10 nH series inductance. Series resistance changes with each inductance from 5 Ω to 35 Ω with 10 Ω steps

Any additional parasitic inductance is critical if we try to measure D2D events with a measurement setup. There is typically additional inductance if we use a pogo pin to discharge a charged component. For example, a CDM tester has about 10 nH series inductance to fulfill the current waveform shape defined in calibration requirements [3]. To capture realistic discharge currents that represent D2D events, the measurement system should have less than 1 nH parasitic inductance. On the other hand, for verification measurement purposes, we could use a higher inductance value to compensate for possible variation with the contact resistance.

Discussion

With a higher expected D2D ESD stress, more silicon area would be required for die interface protection. This could become the limiting factor from the die or SoC design point of view due to the high number of protection circuits needed.

When considering the calculation results of this paper, it can be estimated that the potential difference during D2D assembly can be around 2 V – 10 V if dies have more than about 100 pC static charges after pickup. The resulting peak current can be over 1 A. For example, 10 V discharge potential would be at least one decade below a typical IC component CDM rating, but could still initiate a discharge event that can damage sensitive die interfaces with limited on‑chip protection. This largely depends on how much static charge dies have, the physical construction of dies, and how the assembly setup has been realized. The effectiveness of ionization can also affect the final charge and voltage levels found in a real-life assembly environment.

One more open question is how to specify EPA control limits for D2D assembly processes. A voltage limit alone is not valid, as the measured electrostatic potential depends on the capacitance. Discharge current measurements are challenging, especially when done inside the process area. From our experience, it may require multiple attempts to capture the highest discharge current waveform from a charged die with less than 20 V initial potential in a laboratory environment. Here, the contact resistance plays a major role in changing the shape of the current waveform from pulse to pulse.

More challenges come from the die dimensions. Interconnections can have dense 25 μm – 400 μm pitch, making physical ESD testing difficult [2]. Discharge detection with antennas is also challenging due to weak discharge events from small-sized dies with a low initial potential difference. Die charge and potential measurement together would give good information for control purposes, but would require contacting the die with measurement probes inside the assembly equipment.

Conclusion

D2D assembly is made with automated process tools where ESD risks are typically mitigated with ionization and by grounding conductors. However, D2D assembly can still have ESD events after a die charge during pickup and when it is placed on another die, interposer, or IC. Depending on the initial charge and contact resistance, these discharge events can have around 100 mA – 2 A peak current and current rise time from tens of picoseconds above 100 ps.

Based on this study, the contact resistance has a significant effect on the peak current of low-voltage discharges. Other affecting parameters are the initial source capacitance, charge of the die, capacitive coupling, location of the discharge, positioning, internal design of the die, and design of the reference die, IC, or interposer. D2D assembly setup can also alter the discharge current waveform. For example, changing the size or type of the pickup nozzle from conductor to dielectric changes the source capacitance, capacitive coupling, and discharge voltage during the assembly phase.

The required bandwidth to capture D2D discharges is typically more than about 20 GHz. This is due to the low series parasitic inductance in pH scale and source capacitances around ten picofarads. Simulation tools do not have strict bandwidth limitations, but practical D2D ESD current measurements can be challenging to carry out with a wide bandwidth. This also makes it challenging to directly compare measurement and simulation results.

There is no simple method to specify limits for D2D ESD control or for internal interfaces, as the die voltage or charge alone does not specify the discharge current waveform. Similarly, it is challenging to define one safe peak current or rise time limit for interconnection on-chip ESD designs. In addition, CDM tester current measurements may not correlate with real-life D2D discharge events due to different discharge scenarios. Finding a more suitable measurement method for D2D events requires more research.

References

L. Peters, “Enabling Test Strategies For 2.5D, 3D Stacked ICs,” Semiconductor Engineering, September 8, 2022.
Z. Zhi Li, “Scaling Solder Micro-Bump Interconnect Down to 10 μm Pitch for Advanced 3D IC Packages,” 2021 IEEE 71st Electronic Components and Technology Conference (ECTC), DOI: 10.1109/ ECTC32696.2021.00082,
P. Tamminen, J. Smallwood, W. Stadler, “The Main Parameters Affecting Charged Device Discharge Waveforms in a CDM Qualification and Manufacturing,” 2017 39^th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), September 10-14, 2017.
D. Johnsson, P. Tamminen, H. Gossner, T. Viheriäkoski, “Peak Currents of Low CDM Die-to-Die Discharges,” 2023 45^th Annual EOS/ESD Symposium (EOS/ESD), October 2-4, 2023.
P. Tamminen, “Charge distribution and discharge current analysis with charged connector pins,” Electrostatics, 2019.
T. Maloney, N. Jack, “CDM Tester Properties as Deduced from Waveforms,” IEEE Transactions on Device and Materials Reliability, Volume 14, Issue 3, September 2014.
E. Hourdakis, B. J. Simonds, N. M. Zimmerman, “Submicron Gap Capacitor for Measurement of Breakdown Voltage in Air,” Review of Scientific Instruments, Volume 77, Issue 034702, March 24, 2006.
A. Peschot, N. Bonifaci, O. Lesaint, “Deviations from the Paschen’s Law at Short Gap Distances from 100 nm to 10 mm in Air and Nitrogen,” Applied Physics Letters, 105, 123109, 2014.
R.H. Fowler, L. Nordheim, “Electron Emission in Intense Electric Fields,” Proceedings of the Royal Society A, Volume 119, Issue 781, May 1, 1928.
I.A. Ivanov, I.G. Kiselev, S.V. Urushev, “The Transient Electric Resistance of Contacts Taking the Surface Roughness into Account,” Russian Electrical Engineering, Volume 88, October 2017.
ASME B46.1-2019, Surface Texture (Surface Roughness, Waviness, and Lay), American Society of Mechanical Engineers [ASME].
P. Tamminen, T. Viheriäkoski, “Characterization of ESD Risks in an Assembly Process by Using Component-Level CDM Withstand Voltage“, 2007 29^th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), September 16-21, 2007.
A. Jahanzeb, Y-Y. Lin, S. Marum, J. Schichl, C. Duvvury, “CDM Peak Current Variations and Impact Upon CDM Performance Thresholds,” 2007 29^th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), September 16-21, 2007.

Share this story:

Pasi Tamminen is an EMC specialist at Danfoos Drives in Pirkanmaa, Finland, and has conducted extensive research on electrostatics, EMC/ESD failures, and system qualifications throughout his 25-plus career. Tamminen is also actively involved in IEC and ANSI standardization efforts. He can be reached at pasi.tamminen@danfoos.com.

Toni Viheriäkoski is the owner of Cascade Metrology in Lohja, Uusimma, Finland, which focuses on electrostatics and ESD risk analysis for clients in the healthcare, medical, electronics, automotive, and process industries. He has served as the chair of the Finnish STAHA Association since 2006, and is a member of WG17 and WG25 of the EOS/ESD Association. Viheriäkoski can be reached at toni.viheriakoski@cascademetrology.com.

Back to Issue