Basing CDM ESD Test Goals on Fundamental Limits

Close-up of a bright, branching electrostatic discharge (ESD) spark emitting from the tip of a metal probe against a blurred background.

Knowing Worst-Case Limits Helps Set CDM Test Goals Based on Use Conditions

hen we mention the charged device model (CDM) in electrostatic discharge (ESD), we could be referring to the essential factory event (referred to in this text as ChDE, or charged device event), or to the simulated event in a CDM tester, JS-002 in particular (see Reference 1).

A recent publication (Reference 2) used radial transmission line (RTL) theory to formulate the most accurate analytical model yet for these two versions of CDM, whereby a charged circular plate discharges at its center into a ground plate, as shown in Figure 1. RTL theory captures the essentials of both CDM cases and applies best to the real-world or actual use condition ChDE, again in Figure 1, representing component handling and die attach operations almost perfectly.

Figure 1: Typical CDM event configuration. We model a device of area A as being an equivalent circular disk above a ground plane.

In this article, we will use the basic results of RTL theory to find out how severe CDM events (i.e., ChDE) might be for devices of a given size. This will help address what our true CDM test expectations for the devices should be, as there is very little guidance on how much CDM performance is “good” or “enough,” based on use conditions and device dimensions. Particularly with the introduction of more reproducible, spark-free, contact-first, CDM-like tests, we will want to specify criteria, such as peak current I_pk, along with rise time and slew rate (A/nsec of rising current edge), that would be acceptable as a CDM test for a given device, irrespective of the exact method used.

Many years of failure analysis after CDM testing, and correlation with factory failures, have convinced us that I_pk is the strongest indicator of a failure threshold from the measured waveform, as long as charge Q in the main pulse flows within a time scale (nanosecond or sub‑nanosecond) appropriate to the device size. Beyond that, rise times and slew rates are sometimes cited in reference to oxide failures because of the sharp rising edge of the pulse.

It therefore makes sense to have some minimum expectations, probably for slew rate rather than rise time. Like I_pk, slew rate scales with Q or surface electric field E_⊥, while minimum rise time is more a measure of the wave propagation time across the device, so small devices have fast rise time, due to reflection from the boundary. Slew rate depends only weakly on device size and scales with Q or E_⊥.

As described in Reference 2 and pictured in Figure 2, the RTL model has only vertical E-field E_z and axial H-field H_φ, with no fringing fields. This results in a simple but effective first approximation of capacitance:

and inductance

where r_i is the inner disk radius (probe or spark channel), r_o the outer radius, and d the plate separation. Equation 1 is the familiar parallel-plate capacitance formula, where we use other resources to estimate the equivalent outer radius r_o due to fringing fields and possible non-circular geometry. Equation 2 is a simple model of inductance, not usually seen in CDM work until discussed in Reference 2, based on boundary conditions for current at the inner radius (conducting probe or spark channel) and at the plate boundaries. It is fairly accurate for d << r_o, exactly what we expect for component handling or die attach.

Figure 2: Side view of RTL current flow and field pattern for open circuit at periphery (outward wave vectors). The current flows through the spark channel in the middle for events such as in Figure 1.

In this article, the spark channel r_i will be presumed to be no larger than 10 μm (it is usually smaller) and a negligible influence on die or component capacitance.

In the RTL model, the LC product, and thus ω₀, is insensitive to the plate separation d, as also seen in the product of Equations 1 and 2. This property is important and leads us into our subject here, worst-case considerations of the factory ChDE

We start with the basic 2-pole underdamped decaying exponential solution for peak current, developed for a 2014 paper (see Reference 3) in these terms:

C is capacitance, V₀ is voltage (thus Q = CV₀), L is inductance, and D is damping factor RC/(2√LC) or RCw₀/2. I_pk is highest for D = 0, so I_pk can be no higher than Qω₀, rise time no faster than 1/w₀, and slew rate (A/nsec of rising current edge) no faster than Qw₀². These are the fundamental limits that we will use as we work toward arriving at reasonable CDM performance expectations for devices of a certain size, under expected use conditions.

At this point, we’re nearly ready to calculate I_pk and other limits as a function of effective outer radius and fundamental constants relating to wave propagation. Equations 1-3 give us an estimate of worst-case w₀ = 1/√LC, leaving only charge Q to determine the important parameters (I_pk= Qw₀, slew rate = Qw₀²) for a given size, i.e., equivalent radius r₀.

The results presented in Reference 2 show that, after solving the RTL problem with circular Bessel functions, the estimates from Equations 1-3 need only a slight adjustment for parameter α in the following:

where τ₀ = r₀/c, c the speed of light. While Equations 1 and 2 would give α = √2/2=0.707…, the detailed RTL solution and analysis in Reference 2 find that 0.6433 < a < 0.7064, so our worst case is with α=0.6433. This fixes the scaling for I_pk, rise time (= 1/w₀, the 1 radian time being the 10-90% rise time for a sinusoid), and slew rate. Now we turn to charge Q to complete the calculation.

Under use conditions (ChDE), the charge Q caused by CDM events could be due to tribocharging or to external fields from charged surfaces, resulting in induced charge on the component or die. In either case, field meters are employed in the factory to keep CDM events under control, so the goal is to keep E-fields below some achievable value. Here, we will use E = 100 V/cm as a goal and show that Q scales linearly with field. As Gauss’s Law relates surface charge density σ to perpendicular field through σ = ε₀E_⊥, we find that:

thus worst-case

when we put in the lowest value of α. This I_pk limit is plotted in Figure 3 for E_⊥ = 100V/cm, while minimum rise time ≥ 1/ω₀, from Equation 4, appears in Figure 4.

Figure 3: Worst-case peak current vs. area (pr02); scales linearly with electric field E⊥

Figure 3: Worst-case peak current vs. area (πr₀²); scales linearly with electric field E_⊥

Figure 4: Minimum rise time vs. area, for a spark channel of radius r_i = 10 µm

Both are plotted in terms of equivalent area A=πr₀², corresponding to the die or package size. The slew rate limit, nearly independent of A, is:

again plotted vs. A and with E_⊥ =100V/cm, in Figure 5.

Figure 5: Worst-case slew rate; scales with E_⊥ with weak dependence on area

The same data for I_pk and slew rate are plotted in Figure 6, showing a boundary in the I_pk-slew rate plane beyond which (above and to the right) one would want to achieve passing CDM test results, in order to assure robustness beyond the limits. As E_⊥ varies, the scales shrink by the same factor. Conversely, one could think of a passing test result beyond the boundary as “clearing” the component to a higher E_⊥ value, one for I_pk and one for slew rate. We expect that for a given E_⊥, we will have to use a higher I_pk value to achieve the desired slew rate, therefore, the E_⊥ goals for I_pk can be higher than for slew rate.

Figure 6: Maximum slew rate-peak current boundary curve for E_⊥= 100V/cm. A “good” device would be one that passes CDM testing above and to the right of the curve.

All CDM events are weakened by spark resistance, affecting the 2-pole damped sinusoid model through damping factor D, as seen in Equation 3 for I_pk, in the exponential factor. Once we are confident of a minimum D, worst-case I_pk degrades from the D=0 value (for any area A, as in Figure 3) as plotted in Figure 7.

Figure 7: Reduction of Ipk and slew rate worst case due to damping factor D = RCw0/2

Figure 7: Reduction of I_pk and slew rate worst case due to damping factor D = RCw₀/2

Slew rate also degrades with D, although not as strongly, as also seen in Figure 7. For the slew rate vs. D, we use the I_pk value as reduced by D in Equation 3, then divide that by rise time t_r, as derived from the general two pole solution in Reference 3, Appendix B, for the peak current time t₀. We then take 2t₀/π as the D-dependent rise time, in order to match up with D = 0 slew rate as in Equation 7 and reflecting the actual rise time. This is:

From a vast number of observed CDM waveforms, we find that the “cleanest” pulses, with low spark resistance, result in D no less than 0.25-0.3. Therefore, D = 0.2 would be a conservative value to use for reducing I_pk and slew rate goals. This means we could comfortably reduce I_pk to 75% of the D = 0 value and slew rate to 85% of the D = 0 value, even without recognizing that D is larger for larger area (and higher C) devices. The boundary curve of Figure 6 and CDM target goals for given E_⊥ would be affected accordingly.

We now have a clearer idea of how waveform goals of I_pk and slew rate can match up with, say, the test condition goals of JS = 002 (see Reference 1). For example, TC125 in JS-002 asks for about 3A peak current and <350 ps rise time, i.e., about 9 A/nsec slew rate, for the large CDM target (about 5 cm²). Referring to Figures 3-6, a passing result for a 5 cm² device to TC125 would mean clearance of E_⊥ = 500V/cm for I_pk, but of just over 100V/cm if slew rate under test was barely passing. Even so, 100V/cm is considered a reasonable static control goal at present, and it could be reduced further in the future by using more aggressive static control, the kind long used in the manufacture of magnetic tape heads, when needed.

The reader is invited to apply these concepts to the 1 cm² target discussed in Reference 2, II.B.2, surrounding Figures 8 and 9, and adapted from a 2024 study (see Reference 4). Numbers work out very well for rise time, slew rate, and I_pk limits, using D = 0.3, and if √LC is computed from the circuit modeled waveform values. Evidently, L is reduced by the 2 mm diameter pedestal for discharge, artificially suppressing some of the magnetic field that slows things down. The equivalent field from this tribocharged device (no static control applied, maximum tool speed) is 376V/cm.

Conclusion

In conclusion, we hope that the study discussed in this article helps prepare the design and test community for setting future CDM test goals for products that will be exposed to CDM events in manufacturing and use. We have tried to show how goals should center around peak current and slew rate, and how CDM testing can align those waveform properties with use conditions.

References

ANSI/ESDA/JEDEC JS-002-2025, Charged Device Model (CDM)-Device Level test standard, July 2025.
T.J. Maloney, “Radial Transmission Line Effects in Charged Device Model Events and Testing,” 2025 EOS/ESD Symposium, Riverside, CA, September 15-17, 2025, paper 4A.2.
T. Maloney and N. Jack, “CDM Tester Properties as Deduced from Waveforms,” IEEE TDMR-14, pp. 792-800, 2014.
E. Jirutkova, H. Wolf, H. Gieser, “In-situ ESD Current Sensing in a Pick and Place Machine,” 2024 EOS/ESD Symposium, Reno, NV, paper M1.1.

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The Authors
Timothy J. Maloney is a Fellow of the IEEE and the co-author of the book, Basic ESD and I/O Design (Wiley, 1998). He spent much of his 40-plus-year career as a Senior Principal Engineer at Intel Corporation. Maloney can be reached at tjmaloney@sbcglobal.net.

Peyman Ensaf is a Principal Electromagnetic Effects Engineer at Boeing and can be reached at peyman.ensaf@boeing.com.

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