Heel straps remain the default in most factories. They are inexpensive, easy to deploy, and reliably pass basic resistance checks. In qualification testing, test subjects may not represent how people actually walk, masking inconsistent results that depend heavily on individual gait. Research in gait analysis shows ~ 60–65% of individuals maintain consistent heel-first contact, while 8–12% are habitual forefoot or toe walkers, meaning their heel straps may never touch the floor. ANSI/ESD STM 97.2 lab experiments show floor peak voltages ranging from <30 volts on conductive rubber to >200 volts on conductive vinyl and epoxy, depending on footwear, partially covered by a strap. Without continuous contact as people walk, charge accumulates and cannot discharge until the strap touches the floor.

Full-coverage sole straps and ESD shoes address the core deficiency of heel straps: minimal, inconsistent contact with the floor. Sole straps extend conductive material across both heel and forefoot, engaging the flooring throughout the entire stance phase rather than at a single point, significantly improving continuity and reducing walking-voltage fluctuations. ESD shoes further enhance reliability by integrating conductive elements into the outsole and midsole, eliminating common human failures such as misaligned straps, worn contact patches, or improper fit.

Footwear and flooring must always be evaluated as a system. Most ESD floors are roughly 95% insulative, with grounding achieved through conductive granules or carbon veins. These surfaces generate static during movement and rely on footwear contact for discharge, making a strong case for low-generating floor materials.

Selecting the right ESD flooring has a disproportionate impact on engineering outcomes because the floor is the foundation of all grounding within an EPA, excluding the work surface. The floor establishes the reference plane that personnel, carts, chairs, fixtures, and mobile equipment must couple to. Programs that focus narrowly on personnel grounding while overlooking wheels, casters, seating, and maintenance pathways often create hidden voltage differentials within the EPA.

Flooring selection also directly influences the walking-voltage component of ANSI/ESD S20.20, the parameter most closely tied to real-world ESD failures. High-generating or finish-dependent floors introduce variability, maintenance burden, and long‑term instability. Low-generating, maintenance-stable ESD floors like conductive rubber provide consistent charge control, predictable process behavior, and common electrical potential across the entire environment, conditions essential for reliable high‑yield manufacturing.

here are lots of different ESD testing standards out there, and most of them have a schematic similar to the one above from MIL‑STD‑461G. However, if you look across multiple standards, you’ll see that Rd and Cd can have different values. I recently had an aerospace client who would normally test to CS118 from the MIL-STD. But, due to a particular threat environment, we recommended applying a harsher test from the automotive world. CS118 has a maximum test at ±15 kV, but we thought a ±25 kV test would be appropriate.

In looking at ISO 10605 to remind myself of the parameters of the ±25 kV discharge, I was reminded that Rd and Cd vary with different tests, and I wanted to make sure that I was using the appropriate value. The ISO standard has two options for both the resistor and capacitor. The cap can be 150 or 330 pF, and the resistor can be 330 or 2000 Ω. Thanks to these values being standard in both ISO and IEC 61000‑4-2, they can be found in most off-the-shelf ESD guns. So, which values should you use if you’re testing beyond a specific standard?

apacitors play a crucial role in reducing electromagnetic interference (EMI) by acting as filters that block unwanted high-frequency noise while allowing the desired signal to pass through. They achieve this by storing and releasing electrical energy, which helps to smooth out voltage fluctuations and suppress noise. Capacitors are often used in conjunction with inductors to form LC filters, which are effective in attenuating EMI across a wide range of frequencies.

n previous issues [1-3], we have established the need for HIRF testing and the field strengths that equipment needs to survive. But how are these levels used to test the aircraft? How do they relate to the test levels found in DO-160 and other standards?

The SAE has a series of aerospace recommended practices (ARPs) used for the certification of aircraft and to support FAA Advisory Circulars. Two we will look at are ARP60493, Guide to Civil Aircraft Electromagnetic Compatibility (EMC), and ARP5583A, Guide to Certification of Aircraft in a High-Intensity Radiated Field (HIRF) Environment, which is intended to be “consistent with the certification steps described in AC 20-158.” [4]

Electronic Warfare:

ver the past decade, preeminent countries involved in major military conflicts mainly focused on asymmetrical warfare—surprise attacks by small groups armed with modern, high‑tech weaponry. During that same period, however, near‑peer adversaries began attaining impressive electronic warfare (EW) capabilities. As a result, a plethora of new, dynamic threats flooded the EW spectrum, pushing threat detection and analysis to keep pace.

Large military forces must now engage in ongoing development and evolution to stay ahead of their adversaries, leading to a need for a more flexible, scalable approach to threat detection, analysis, and response.

n the 21st century, artificial intelligence (AI) technology has been driving a paradigm shift in defense, particularly by significantly enhancing operational capabilities in the air force domain. AI-powered combat systems support a wide range of functions such as target detection, tactical decision-making, situational awareness, and autonomous flight, thereby reducing the cognitive burden on human pilots and improving real-time responsiveness and survivability. However, the increasing autonomy of AI systems introduces complex challenges, including potential violations of international law, decision-making errors, and ambiguous attribution of ethical responsibility. This has led to a growing need to redefine the role of human fighter pilots within AI-integrated operations. To address these issues, this study proposes a quantitative ethical decision-making model that mathematically integrates national military ethics principles and international legal norms, while incorporating dynamic battlefield variables. The proposed model aims to contribute to defense policy development and combat training systems by offering a structured and operationally applicable ethical evaluation framework.

SD protection devices designed to safeguard sensitive high-speed interfaces must meet stringent signal integrity requirements. As bandwidth demand increases, these devices require increasingly lower capacitance, as shown in Figure 1. However, with the rise of high-speed applications like HDMI 2.2 and USB 4, ESD solutions should not only have smaller capacitance but must also be designed with robust signal integrity practices to ensure compliance with stringent performance standards.

Accurate and reliable measurements are vital to verify the compliance of ESD devices with interface standards, and it is critical that the measurements are not distorted by the measurement setup. In this article, we will focus on S-parameter measurements, which are widely used to characterize the high-frequency behaviour of ESD devices. As the capacitance of ESD protection devices continues to shrink into the femtofarad range, the influence of the measurement PCB and its layout on S-parameter results becomes increasingly significant.

his is the first of several columns investigating the effectiveness of decoupling capacitors while varying the topology of vias, trace length between the decoupling capacitor and the integrated circuit (IC) power/ground pins, and distance from the internal power and ground plane pair. Specifically, the impact of the PCB geometry will be evaluated by performing RF Emission testing on six PCB variants, according to the CISPR 25 standard. Part 1 of this study defines the board topologies and the PCB circuitry. The following parts will show the RF Emissions results.

his column is the second in a three-part series on testing small form factor products for CDM. Part 1 highlighted the issues of CDM testing with the current field-induced CDM (FICDM) testers. The main problems are the pogo pin size vs package or ball bump size and that small form factor products may have very low withstand voltages, where the FICDM testers are known to be unreliable. In Part 2, the first set of possible solutions is presented. These solutions are air discharge techniques just like FICDM. Part 3 will focus on contact-first methods to address these same issues.

Air Discharge Options for Bare Die and Interface Die Testing